Page MenuHomePhabricator

[TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V
ClosedPublic

Authored by asb on Oct 8 2018, 3:33 AM.

Details

Summary

DAGTypeLegalizer::PromoteSetCCOperands currently prefers to zero-extend operands when it is able to do so. For some targets this is more expensive than a sign-extension, which is also a valid choice. Introduce the isSExtCheaperThanZExt hook and use it in the new SExtOrZExtPromotedInteger helper. On RISC-V, we prefer sign-extension for FromTy == MVT::i32 and ToTy == MVT::i64, as it can be performed using a single instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

asb created this revision.Oct 8 2018, 3:33 AM
asb updated this revision to Diff 168635.Oct 8 2018, 3:34 AM

Update to attache the correct diff this time.

lewis-revill added inline comments.
lib/Target/RISCV/RISCVISelLowering.cpp
274 ↗(On Diff #168635)

Should

if (!Subtarget.is64Bit())
    return false;

be added here? i64 shouldn't make it this far on 32 bit but is it better to be explicit?

Makes sense.

lib/CodeGen/SelectionDAG/LegalizeTypes.h
284 ↗(On Diff #168635)

This probably needs a doc-comment explaining that for a given subtarget and type, the choice of either sign-extension or zero-extension is consistent.

asb updated this revision to Diff 169521.Oct 12 2018, 4:41 PM
asb marked 2 inline comments as done.

Update to address review comments (thanks!).

This revision is now accepted and ready to land.Oct 12 2018, 5:11 PM
This revision was automatically updated to reflect the committed changes.