[WebAssembly] any_true and all_true intrinsics and instructions

[tlively]

• Remove unused FileCheck lines

[aheejin]

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

961

Nit: maybe a newline here for readability?

[aheejin]

Is there any reason why intrinsic names don't have underscores like anytrue but instruction names do, like any_true?

[tlively]

In D52755#1253324, @aheejin wrote:

Is there any reason why intrinsic names don't have underscores like anytrue but instruction names do, like any_true?

Underscores in intrinsic tablegen names are turned into dots at the IR level. I liked anytrue better than any.true.

[tlively]

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

961

Done in D52813 to avoid annoying rebases.

[aheejin]

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

200 ↗

(On Diff #168060)

Sorry, but the indentation looks like it should have one more whitespace here

include/llvm/IR/IntrinsicsWebAssembly.td

Intrinsic<[llvm_i32_ty],
             [IntrInaccessibleMemOrArgMemOnly, ReadOnly<0>, NoCapture<0>,
              IntrHasSideEffects],
              "", [SDNPMemOperand]>;
 def int_wasm_atomic_notify:
   Intrinsic<[llvm_i32_ty], [LLVMPointerType<llvm_i32_ty>, llvm_i32_ty],
             [IntrInaccessibleMemOnly, NoCapture<0>, IntrHasSideEffects], "",
             [SDNPMemOperand]>;
 
-}
+//===----------------------------------------------------------------------===//
+// SIMD intrinsics
+//===----------------------------------------------------------------------===//
+
+def int_wasm_anytrue :
+  Intrinsic<[llvm_i32_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_alltrue :
+  Intrinsic<[llvm_i32_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
+} // TargetPrefix = "wasm"

lib/Target/WebAssembly/WebAssemblyISD.def

 HANDLE_NODETYPE(CALL1)
 HANDLE_NODETYPE(CALL0)
 HANDLE_NODETYPE(RETURN)
 HANDLE_NODETYPE(ARGUMENT)
 HANDLE_NODETYPE(Wrapper)
 HANDLE_NODETYPE(BR_IF)
 HANDLE_NODETYPE(BR_TABLE)
 HANDLE_NODETYPE(SHUFFLE)
+HANDLE_NODETYPE(ANYTRUE)
+HANDLE_NODETYPE(ALLTRUE)
 
 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 
 SDValue
 WebAssemblyTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                    SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc DL(Op);
   switch (IntNo) {
   default:
     return {}; // Don't custom lower most intrinsics.
-
+  case Intrinsic::wasm_anytrue:
+  case Intrinsic::wasm_alltrue: {
+    unsigned OpCode = IntNo == Intrinsic::wasm_anytrue
+                          ? WebAssemblyISD::ANYTRUE
+                          : WebAssemblyISD::ALLTRUE;
+    return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1));
+  }
   case Intrinsic::wasm_lsda:
     // TODO For now, just return 0 not to crash
     return DAG.getConstant(0, DL, Op.getValueType());
   }
 }
 
 SDValue
 WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 //===----------------------------------------------------------------------===//
 
 // constrained immediate argument types
 foreach SIZE = [8, 16] in
 def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">;
 foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
+// Custom nodes for custom operations
+def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
+def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
+def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
+def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
+def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
+
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
   let isMoveImm = 1, isReMaterializable = 1 in
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
                                   "v128.const\t"#args, 0>;
 }
 multiclass SIMDLoad<ValueType vec_t> {
defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
                              (vec_t V128:$dst),
                              (vec_t (xor
                                (vec_t V128:$vec),
                                (vec_t (splat_pat (lane_t -1)))
                              ))
                            )],
                            "v128.not\t$dst, $vec", "v128.not", 63>;
 }
+multiclass SIMDReduceVec<ValueType vec_t, string vec, string name, SDNode op,
+                      bits<32> simdop> {
+  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+                       [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
+                       vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
+}
+multiclass SIMDReduce<string name, SDNode op, bits<32> baseInst> {
+  defm "" : SIMDReduceVec<v16i8, "i8x16", name, op, baseInst>;
+  defm "" : SIMDReduceVec<v8i16, "i16x8", name, op, !add(baseInst, 1)>;
+  defm "" : SIMDReduceVec<v4i32, "i32x4", name, op, !add(baseInst, 2)>;
+  defm "" : SIMDReduceVec<v2i64, "i64x2", name, op, !add(baseInst, 3)>;
+}
 multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
                              string name, CondCode cond, bits<32> simdop> {
   defm _#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
            [(set (out_t V128:$dst),
              (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond))],
            vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
 }

 defm XOR : SIMDBitwise<xor, "xor", 62>;
 } // isCommutable = 1
 
 defm "" : SIMDNot<v16i8, splat16, i32>;
 defm "" : SIMDNot<v8i16, splat8, i32>;
 defm "" : SIMDNot<v4i32, splat4, i32>;
 defm "" : SIMDNot<v2i64, splat2, i64>;
 
+defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
+defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
+
 let isCommutable = 1 in {
 defm EQ : SIMDConditionInt<"eq", SETEQ, 73>;
 defm EQ : SIMDConditionFP<"eq", SETOEQ, 77>;
 defm NE : SIMDConditionInt<"ne", SETNE, 79>;
 defm NE : SIMDConditionFP<"ne", SETUNE, 83>;
 } // isCommutable = 1
 
 defm LT_S : SIMDConditionInt<"lt_s", SETLT, 85, 2>;

 def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
 
 // Truncate i64 shift operands to i32s
 foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in
 def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
           (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
 
 // Shuffles after custom lowering
-def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
-def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 def : Pat<(v16i8 (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
             (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
             (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
             (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
             (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),

test/CodeGen/WebAssembly/simd-intrinsics.ll

+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+
+; Test that SIMD128 intrinsics lower as expected. These intrinsics are
+; only expected to lower successfully if the simd128 attribute is
+; enabled and legal types are used.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; ==============================================================================
+; 16 x i8
+; ==============================================================================
+; CHECK-LABEL: any_v16i8:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
+define i32 @any_v16i8(<16 x i8> %x) {
+  %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
+  ret i32 %a
+}
+
+; CHECK-LABEL: all_v16i8:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
+define i32 @all_v16i8(<16 x i8> %x) {
+  %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
+  ret i32 %a
+}
+
+; ==============================================================================
+; 8 x i16
+; ==============================================================================
+; CHECK-LABEL: any_v8i16:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
+define i32 @any_v8i16(<8 x i16> %x) {
+  %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
+  ret i32 %a
+}
+
+; CHECK-LABEL: all_v8i16:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
+define i32 @all_v8i16(<8 x i16> %x) {
+  %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
+  ret i32 %a
+}
+
+; ==============================================================================
+; 4 x i32
+; ==============================================================================
+; CHECK-LABEL: any_v4i32:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
+define i32 @any_v4i32(<4 x i32> %x) {
+  %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
+  ret i32 %a
+}
+
+; CHECK-LABEL: all_v4i32:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
+define i32 @all_v4i32(<4 x i32> %x) {
+  %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
+  ret i32 %a
+}
+
+; ==============================================================================
+; 2 x i64
+; ==============================================================================
+; CHECK-LABEL: any_v2i64:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
+define i32 @any_v2i64(<2 x i64> %x) {
+  %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
+  ret i32 %a
+}
+
+; CHECK-LABEL: all_v2i64:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
+define i32 @all_v2i64(<2 x i64> %x) {
+  %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
+  ret i32 %a
+}

test/MC/WebAssembly/simd-encodings.s

# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
     v128.or
 
     # CHECK: v128.xor # encoding: [0xfd,0x3e]
     v128.xor
 
     # CHECK: v128.not # encoding: [0xfd,0x3f]
     v128.not
 
+    # CHECK: i8x16.any_true # encoding: [0xfd,0x41]
+    i8x16.any_true
+
+    # CHECK: i16x8.any_true # encoding: [0xfd,0x42]
+    i16x8.any_true
+
+    # CHECK: i32x4.any_true # encoding: [0xfd,0x43]
+    i32x4.any_true
+
+    # CHECK: i64x2.any_true # encoding: [0xfd,0x44]
+    i64x2.any_true
+
+    # CHECK: i8x16.all_true # encoding: [0xfd,0x45]
+    i8x16.all_true
+
+    # CHECK: i16x8.all_true # encoding: [0xfd,0x46]
+    i16x8.all_true
+
+    # CHECK: i32x4.all_true # encoding: [0xfd,0x47]
+    i32x4.all_true
+
+    # CHECK: i64x2.all_true # encoding: [0xfd,0x48]
+    i64x2.all_true
+
     # CHECK: i8x16.eq # encoding: [0xfd,0x49]
     i8x16.eq
 
     # CHECK: i16x8.eq # encoding: [0xfd,0x4a]
     i16x8.eq
 
     # CHECK: i32x4.eq # encoding: [0xfd,0x4b]
     i32x4.eq