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[AMDGPU] Match v_swap_b32
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Authored by rampitec on Sep 28 2018, 5:36 PM.

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rampitec created this revision.Sep 28 2018, 5:36 PM
rampitec updated this revision to Diff 167773.Oct 1 2018, 10:37 AM

Split off independent D52736.

arsenm added a comment.Oct 1 2018, 7:35 PM

I can see why you would put it in SIShrinkInstructions, but this isn't really a shrinking problem. Can you add a comment that this is really just a generic post-RA peephole that should probably be in a separate pass?

lib/Target/AMDGPU/SIInstrInfo.h
219 ↗(On Diff #167773)

!isReg() and continue to reduce indentation

226–227 ↗(On Diff #167773)

I think this is a bit difficult to read with the () and .any() on the temporary. Can you use a variable for the &

234–238 ↗(On Diff #167773)

How is this different from MachineInstr::readsRegister? Does that just to add a subreg operand?

246–247 ↗(On Diff #167773)

RegSubRegPair instead of std::pair?

286 ↗(On Diff #167773)

use_nodbg_operands?

401 ↗(On Diff #167773)

ST.hasSwap() or something implemented by checking gfx9-insts

test/CodeGen/AMDGPU/v_swap_b32.mir
503

Needs a test where the mov/copy has extra implicit uses / defs. I think this should probably skip them if there are. In particular I'm worried about the super-register copy pattern where there's an implicit def of the super-register on the first copy in the sequence

rampitec marked 5 inline comments as done.Oct 1 2018, 9:44 PM
rampitec added inline comments.
lib/Target/AMDGPU/SIInstrInfo.h
234–238 ↗(On Diff #167773)

Yes, reads/modifiesRegister would return true if a super-register is modified even if a particular lane of interest does not. Some of the foldings in the test would fail if I use it.

rampitec updated this revision to Diff 167882.Oct 1 2018, 9:45 PM
rampitec marked an inline comment as done.

Addressed review comments.

arsenm added inline comments.Oct 2 2018, 7:53 PM
lib/Target/AMDGPU/AMDGPUSubtarget.h
519

There's a specific GFX9Insts feature (although we have some others that should be checking it instead of the generation already)

lib/Target/AMDGPU/SIInstrInfo.h
234–238 ↗(On Diff #167773)

This needs a comment explaining it then

286 ↗(On Diff #167773)

I still see it as use_operands?

test/CodeGen/AMDGPU/v_swap_b32.mir
521

%2 needs another use which might break

rampitec marked 2 inline comments as done.Oct 19 2018, 3:57 PM
rampitec added inline comments.
lib/Target/AMDGPU/SIInstrInfo.h
286 ↗(On Diff #167773)

You are somehow looking at the old patch.

test/CodeGen/AMDGPU/v_swap_b32.mir
521

What can be a valid implicit use for a COPY besides exec?

rampitec updated this revision to Diff 170272.Oct 19 2018, 3:57 PM
rampitec updated this revision to Diff 170763.Oct 23 2018, 3:10 PM

Relaxed match to allow multiple uses of temp register and keep initial mov to temp:

mov t, x
mov x, y
mov y, t

>

mov t, x (t is potentially dead and move eliminated)
v_swap_b32 x, y

The code LGTM; don't know about the question on the tests.

arsenm accepted this revision.Oct 27 2018, 12:31 PM

LGTM

This revision is now accepted and ready to land.Oct 27 2018, 12:31 PM
This revision was automatically updated to reflect the committed changes.