Currently it returns incorrect operand size for a target independet
node such as COPY if operand is a register with subreg. Instead of
correct subreg size it returns a size of the whole superreg.
Details
Diff Detail
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- rL LLVM
Event Timeline
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | I think this silently will break if we start using 16-bit subregs. Can you assert that this number is consistent with the size of the super-reg? |
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | In fact a lot will break if we start using 16 bit subregs. I would like to add the assert, but that is exactly the problem, one cannot know subreg's size without assuming target specific subreg layout. I.e. I do not see how to do it w/o listing all possible subregs in our target. Also note that MRI.getMaxLaneMaskForVReg() will happily return -1 for the whole register. Any ideas? |
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | You can just assert against the size of the subreg class? Something like (getRegSizeInBits(getSubClassWithSubReg(getRegClass(Reg)) >= 32)? |
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | A subreg can be sub0_sub1, which will pass the check. |
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | Yes, that should work. The issue is if a subregindex like sub0_lo16 is used |
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h | ||
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735–736 | As long as you are not planning to have sub0_lo16_hi16 ;) I see the point, at least cases will fail, which is sufficient to catch. |
I think this silently will break if we start using 16-bit subregs. Can you assert that this number is consistent with the size of the super-reg?