[ARM][v8.5A] Add speculation barriers SSBB and PSSBB

[olista01]

Summary

This adds two new barrier instructions which can be used to restrict
speculative execution of load instructions.

Patch by Pablo Barrio!

[t.p.northover]

This looks fine too after the AArch64 clarification.

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

 
 //===----------------------------------------------------------------------===//
 // Assembler aliases
 //
 
 // Memory barriers
 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
+def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>;
+def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>;
 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
 // Armv8-R 'Data Full Barrier'
 def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>;
 
 // System instructions
 def : MnemonicAlias<"swi", "svc">;
 
 // Load / Store Multiple

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def : t2InstAlias<"teq${p} $Rn, $Rm",
                   (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
 def : t2InstAlias<"tst${p} $Rn, $Rm",
                   (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
 
 // Memory barriers
 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
+
+// Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where
+// 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR".
+def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
+def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
+
 // Armv8-R 'Data Full Barrier'
 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
 
 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
 // width specifier.
 def : t2InstAlias<"ldr${p} $Rt, $addr",
                   (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
 def : t2InstAlias<"ldrb${p} $Rt, $addr",

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
       Mnemonic == "vmovx" || Mnemonic == "vins" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
-      Mnemonic == "sb") {
+      Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
+      Mnemonic == "pssbb") {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
     // Some instructions are only predicable in Thumb mode
     CanAcceptPredicationCode =
         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
                                                "predicable, but condition "
                                                "code specified");
     if (Imm8 == 0x14 && Pred != ARMCC::AL)
       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
                                                "predicable, but condition "
                                                "code specified");
     break;
   }
+  case ARM::DSB:
+  case ARM::t2DSB: {
+
+    if (Inst.getNumOperands() < 2)
+      break;
+
+    unsigned Option = Inst.getOperand(0).getImm();
+    unsigned Pred = Inst.getOperand(1).getImm();
+
+    // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
+    if (Option == 0 && Pred != ARMCC::AL)
+      return Error(Operands[1]->getStartLoc(),
+                   "instruction 'ssbb' is not predicable, but condition code "
+                   "specified");
+    if (Option == 4 && Pred != ARMCC::AL)
+      return Error(Operands[1]->getStartLoc(),
+                   "instruction 'pssbb' is not predicable, but condition code "
+                   "specified");
+    break;
+  }
   case ARM::VMOVRRS: {
     // Source registers must be sequential.
     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
     if (Sm1 != Sm + 1)
       return Error(Operands[5]->getStartLoc(),
                    "source operands must be sequential");
     break;

llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

if (MRC.contains(Reg)) {
       return;
     }
     break;
   }
   case ARM::TSB:
   case ARM::t2TSB:
     O << "\ttsb\tcsync";
     return;
+  case ARM::t2DSB:
+    switch (MI->getOperand(0).getImm()) {
+    default:
+      if (!printAliasInstr(MI, STI, O))
+        printInstruction(MI, STI, O);
+      break;
+    case 0:
+      O << "\tssbb";
+      break;
+    case 4:
+      O << "\tpssbb";
+      break;
+    }
+    printAnnotation(O, Annot);
+    return;
   }
 
   if (!printAliasInstr(MI, STI, O))
     printInstruction(MI, STI, O);
 
   printAnnotation(O, Annot);
 }
 

llvm/trunk/test/MC/ARM/basic-arm-instructions.s

 @ CHECK: dsb  #0xc                    @ encoding: [0x4c,0xf0,0x7f,0xf5]
 @ CHECK: dsb  ish                     @ encoding: [0x4b,0xf0,0x7f,0xf5]
 @ CHECK: dsb  ishst                   @ encoding: [0x4a,0xf0,0x7f,0xf5]
 @ CHECK: dsb  #0x9                    @ encoding: [0x49,0xf0,0x7f,0xf5]
 @ CHECK: dsb  #0x8                    @ encoding: [0x48,0xf0,0x7f,0xf5]
 @ CHECK: dsb  nsh                     @ encoding: [0x47,0xf0,0x7f,0xf5]
 @ CHECK: dsb  nshst                   @ encoding: [0x46,0xf0,0x7f,0xf5]
 @ CHECK: dsb  #0x5                    @ encoding: [0x45,0xf0,0x7f,0xf5]
-@ CHECK: dsb  #0x4                    @ encoding: [0x44,0xf0,0x7f,0xf5]
+@ CHECK: pssbb                          @ encoding: [0x44,0xf0,0x7f,0xf5]
 @ CHECK: dsb  osh                     @ encoding: [0x43,0xf0,0x7f,0xf5]
 @ CHECK: dsb  oshst                   @ encoding: [0x42,0xf0,0x7f,0xf5]
 @ CHECK: dsb  #0x1                    @ encoding: [0x41,0xf0,0x7f,0xf5]
-@ CHECK: dsb  #0x0                    @ encoding: [0x40,0xf0,0x7f,0xf5]
+@ CHECK: ssbb                           @ encoding: [0x40,0xf0,0x7f,0xf5]
 
 @ CHECK: dsb  #0x8                    @ encoding: [0x48,0xf0,0x7f,0xf5]
 @ CHECK: dsb  nsh                     @ encoding: [0x47,0xf0,0x7f,0xf5]
 
 @ CHECK: dsb  sy                      @ encoding: [0x4f,0xf0,0x7f,0xf5]
 @ CHECK: dsb  st                      @ encoding: [0x4e,0xf0,0x7f,0xf5]
 @ CHECK: dsb  ish                     @ encoding: [0x4b,0xf0,0x7f,0xf5]
 @ CHECK: dsb  ish                     @ encoding: [0x4b,0xf0,0x7f,0xf5]

llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

 @ CHECK: dsb  #0xc                    @ encoding: [0xbf,0xf3,0x4c,0x8f]
 @ CHECK: dsb  ish                     @ encoding: [0xbf,0xf3,0x4b,0x8f]
 @ CHECK: dsb  ishst                   @ encoding: [0xbf,0xf3,0x4a,0x8f]
 @ CHECK: dsb  #0x9                    @ encoding: [0xbf,0xf3,0x49,0x8f]
 @ CHECK: dsb  #0x8                    @ encoding: [0xbf,0xf3,0x48,0x8f]
 @ CHECK: dsb  nsh                     @ encoding: [0xbf,0xf3,0x47,0x8f]
 @ CHECK: dsb  nshst                   @ encoding: [0xbf,0xf3,0x46,0x8f]
 @ CHECK: dsb  #0x5                    @ encoding: [0xbf,0xf3,0x45,0x8f]
-@ CHECK: dsb  #0x4                    @ encoding: [0xbf,0xf3,0x44,0x8f]
+@ CHECK: pssbb                          @ encoding: [0xbf,0xf3,0x44,0x8f]
 @ CHECK: dsb  osh                     @ encoding: [0xbf,0xf3,0x43,0x8f]
 @ CHECK: dsb  oshst                   @ encoding: [0xbf,0xf3,0x42,0x8f]
 @ CHECK: dsb  #0x1                    @ encoding: [0xbf,0xf3,0x41,0x8f]
-@ CHECK: dsb  #0x0                    @ encoding: [0xbf,0xf3,0x40,0x8f]
+@ CHECK: ssbb                           @ encoding: [0xbf,0xf3,0x40,0x8f]
 
 @ CHECK: dsb  sy                      @ encoding: [0xbf,0xf3,0x4f,0x8f]
 @ CHECK: dsb  st                      @ encoding: [0xbf,0xf3,0x4e,0x8f]
 @ CHECK: dsb  ish                     @ encoding: [0xbf,0xf3,0x4b,0x8f]
 @ CHECK: dsb  ish                     @ encoding: [0xbf,0xf3,0x4b,0x8f]
 @ CHECK: dsb  ishst                   @ encoding: [0xbf,0xf3,0x4a,0x8f]
 @ CHECK: dsb  ishst                   @ encoding: [0xbf,0xf3,0x4a,0x8f]
 @ CHECK: dsb  nsh                     @ encoding: [0xbf,0xf3,0x47,0x8f]

llvm/trunk/test/MC/ARM/csdb-errors.s

-// RUN: not llvm-mc -triple   armv8a-none-eabi %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s
-
-  it eq
-  csdbeq
-// CHECK: error: instruction 'csdb' is not predicable, but condition code specified

llvm/trunk/test/MC/ARM/csdb.s

-@ RUN:     llvm-mc -triple   armv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=ARM
-@ RUN:     llvm-mc -triple thumbv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=THUMB
-@ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-  csdb
-@ ARM:   csdb   @ encoding: [0x14,0xf0,0x20,0xe3]
-@ THUMB: csdb   @ encoding: [0xaf,0xf3,0x14,0x80]
-@ ERROR: error: instruction requires: thumb2

llvm/trunk/test/MC/ARM/speculation-barriers-errors.s

+// RUN: not llvm-mc -triple   armv8a-none-eabi %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s -check-prefix=THUMB
+
+  it eq
+  csdbeq
+
+  it eq
+  ssbbeq
+
+  it eq
+  pssbbeq
+
+  it eq
+  hinteq #20
+
+  it eq
+  dsbeq #0
+
+  it eq
+  dsbeq #4
+
+// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
+// CHECK: error: instruction 'ssbb' is not predicable, but condition code specified
+// CHECK: error: instruction 'pssbb' is not predicable, but condition code specified
+// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
+// CHECK: error: instruction 'dsb' is not predicable, but condition code specified
+// CHECK: error: instruction 'dsb' is not predicable, but condition code specified
+
+// THUMB: error: instruction 'csdb' is not predicable, but condition code specified
+// THUMB: error: instruction 'ssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'pssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'csdb' is not predicable, but condition code specified
+// THUMB: error: instruction 'ssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'pssbb' is not predicable, but condition code specified

llvm/trunk/test/MC/ARM/speculation-barriers.s

+@ RUN:     llvm-mc -triple   armv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=ARM
+@ RUN:     llvm-mc -triple thumbv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=THUMB
+@ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+csdb
+ssbb
+pssbb
+
+@ ARM:   csdb   @ encoding: [0x14,0xf0,0x20,0xe3]
+@ ARM:   ssbb   @ encoding: [0x40,0xf0,0x7f,0xf5]
+@ ARM:   pssbb  @ encoding: [0x44,0xf0,0x7f,0xf5]
+
+@ THUMB: csdb   @ encoding: [0xaf,0xf3,0x14,0x80]
+@ THUMB: ssbb   @ encoding: [0xbf,0xf3,0x40,0x8f]
+@ THUMB: pssbb  @ encoding: [0xbf,0xf3,0x44,0x8f]
+
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: csdb
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: ssbb
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: pssbb

llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt

 0x5d 0xf0 0x7f 0xf5
 0x5e 0xf0 0x7f 0xf5
 0x5f 0xf0 0x7f 0xf5
 
 #------------------------------------------------------------------------------
 # DSB
 #------------------------------------------------------------------------------
 
-# CHECK: dsb  #0x0
+# CHECK: ssbb
 # CHECK: dsb  #0x1
 # CHECK: dsb  oshst
 # CHECK: dsb  osh
-# CHECK: dsb  #0x4
+# CHECK: pssbb
 # CHECK: dsb  #0x5
 # CHECK: dsb  nshst
 # CHECK: dsb  nsh
 # CHECK: dsb  #0x8
 # CHECK: dsb  #0x9
 # CHECK: dsb  ishst
 # CHECK: dsb  ish
 # CHECK: dsb  #0xc

llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt

 #CHECK: dsb #0xc
 #CHECK: dsb ish
 #CHECK: dsb ishst
 #CHECK: dsb #0x9
 #CHECK: dsb #0x8
 #CHECK: dsb nsh
 #CHECK: dsb nshst
 #CHECK: dsb #0x5
-#CHECK: dsb #0x4
+#CHECK: pssbb
 #CHECK: dsb osh
 #CHECK: dsb oshst
 #CHECK: dsb #0x1
-#CHECK: dsb #0x0
+#CHECK: ssbb
 
 0xbf 0xf3 0x4f 0x8f
 0xbf 0xf3 0x4e 0x8f
 0xbf 0xf3 0x4d 0x8f
 0xbf 0xf3 0x4c 0x8f
 0xbf 0xf3 0x4b 0x8f
 0xbf 0xf3 0x4a 0x8f
 0xbf 0xf3 0x49 0x8f