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[AArch64][v8.5A] Add speculation barriers SSBB and PSSBB
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Authored by olista01 on Sep 25 2018, 7:17 AM.

Details

Summary

This adds two new barrier instructions which can be used to restrict
speculative execution of load instructions.

Patch by Pablo Barrio!

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 created this revision.Sep 25 2018, 7:17 AM
t.p.northover added inline comments.Sep 27 2018, 6:12 AM
lib/Target/AArch64/AArch64InstrInfo.td
648–649 ↗(On Diff #166900)

I think these should have Predicates set since not all CPUs support them.

olista01 added inline comments.Sep 27 2018, 7:40 AM
lib/Target/AArch64/AArch64InstrInfo.td
648–649 ↗(On Diff #166900)

This is deliberate, these instructions have been retroactively added to v8.0-A onwards. This works because they are aliases for "DSB #0" and "DSB #4", which older specs say have to behave like "DSB SY", which has stronger semantics than SSBB and PSSBB. This means that existing cores already implement these, though in a more costly way than v8.5-A allows.

t.p.northover accepted this revision.Sep 27 2018, 8:20 AM

Thanks for the clarification. LGTM.

lib/Target/AArch64/AArch64InstrInfo.td
648–649 ↗(On Diff #166900)

OK, I wondered if it was something like that but the manual was a bit vague on the topic and I wasn't certain the existing DSB sufficed.

This revision is now accepted and ready to land.Sep 27 2018, 8:20 AM
This revision was automatically updated to reflect the committed changes.
llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt