[Intrinsic] Add llvm.minnan and llvm.maxnan instrinsic functions

[tlively]

Summary

These are NaN-propagating versions of llvm.minnum and
llvm.maxnum. These intrinsics lower to the existing fminnan and
fmaxnan instruction selection DAG nodes, so targets that already
support lowering from these nodes should not need to do anything.

WebAssembly in particular requires these intrinsic functions to exist
in order to make its min and max instructions generally available at
the IR level.

[aheejin]

Does this cover all the places we need to handle these new intrinsics? Searching by minnum or maxnum in the llvm directory yields other occurrences in files like lib/Analysis/ValueTracking.cpp, lib/Analysis/VectorUtils.cpp, and lib/Analysis/InstructionSimplify.cpp. (There are more). For test cases as well.

include/llvm/ADT/APFloat.h

1262

Maybe add 1-2 line comments to these two, like other functions?

[tlively]

• Add comments as requested
• Add analogous functionality and tests for every target-independent usage of minnum and maxnum

[dschuff]

docs/LangRef.rst

11596

Does IEEE-754 2018 say anything about which NaN (i.e. is the payload required to be propagated too)?

[sunfish]

docs/LangRef.rst

11596

No, it falls under the general rules for NaN propagation in binary operators (6.2.3). That is, it non-normatively suggests that if two NaN operands are given, one of the payloads be propagated, but it does't give a suggestion as to which.

11599

Another thing that changed in IEEE 754-2018 is that unlike 754-2008's minNum and maxNum, 754-2018's minimum. maximum, minimumNumber, and maximumNumber are defined to treat -0 as if it were less than +0. It'd be nice to adopt this new rule for these new intrinsics, however llvm.minnum already exists and doesn't follow this rule, and existing libm fmin and fmax implementations don't all follow this rule. So, it may not be practical to do so at this time. It'd be useful to mention this discrepancy with the 754-2018 rules here at least though.

[tlively]

• Add notes about exception to IEEE 754-2018 semantics for +0/-0
• Split into multiple commits to make reviewing more pleasant

[tlively]

• Reduce CL to just initial commit, others incoming.

[tlively]

docs/LangRef.rst

11599

Thanks, @sunfish! I've added notes about this.

[tlively]

WebAssembly's handling of +0/-0 *does* match IEEE 754-2018, so these intrinsics (whether target-independent or not) need to be changed to match those semantics as well. I will have to investigate whether the fminnan and fmaxnan ISel DAG nodes are already being used in ways that do not respect these semantics. If they are, we will need new ISel DAG nodes as well.

[sunfish]

In D52450#1248586, @tlively wrote:

WebAssembly's handling of +0/-0 *does* match IEEE 754-2018, so these intrinsics (whether target-independent or not) need to be changed to match those semantics as well. I will have to investigate whether the fminnan and fmaxnan ISel DAG nodes are already being used in ways that do not respect these semantics. If they are, we will need new ISel DAG nodes as well.

It's ok for WebAssembly's semantics to be more constrained than LLVM's. It's the reverse that would be a problem.

[tlively]

In D52450#1248590, @sunfish wrote:

It's ok for WebAssembly's semantics to be more constrained than LLVM's. It's the reverse that would be a problem.

That's true, except that if the semantics of the LLVM intrinsics were not as strict as the semantics of the WebAssembly instructions, then there would be no way for programmers to access WebAssembly's exact semantics at the source level, which is the whole point of implementing these intrinsics at all.

[sunfish]

In D52450#1248681, @tlively wrote:

That's true, except that if the semantics of the LLVM intrinsics were not as strict as the semantics of the WebAssembly instructions, then there would be no way for programmers to access WebAssembly's exact semantics at the source level, which is the whole point of implementing these intrinsics at all.

Oh, right. So in that case, the existing minnum/maxnum intrinsics do have the same problem. That's probably not easy to fix, because it would require changes to existing implementations on other platforms. So we may have to add wasm-specific versions of these intrinsics after all :-/.

[tlively]

In D52450#1248683, @sunfish wrote:

Oh, right. So in that case, the existing minnum/maxnum intrinsics do have the same problem. That's probably not easy to fix, because it would require changes to existing implementations on other platforms. So we may have to add wasm-specific versions of these intrinsics after all :-/.

I don't think adding new intrinsics necessarily means we need to change anything about the old intrinsics. A the C language level, we won't expose builtin functions for wasm that lower to minnum or maxnum, since those don't match wasm semantics. To prevent people from assuming that the only difference between minnum/maxnum and the new intrinsics is NaN propagation, I propose we name the new instrinsics minimum/maximum (after the new IEEE operations) rather than minnan/maxnan.

[tlively]

Abandoned in favor of D52764.

docs/LangRef.rst

 
 Unlike the IEEE-754 2008 behavior, this does not distinguish between
 signaling and quiet NaN inputs. If a target's implementation follows
 the standard and returns a quiet NaN if either input is a signaling
 NaN, the intrinsic lowering is responsible for quieting the inputs to
 correctly return the non-NaN input (e.g. by using the equivalent of
 ``llvm.canonicalize``).
 
+'``llvm.minnan.*``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+This is an overloaded intrinsic. You can use ``llvm.minnan`` on any
+floating-point or vector of floating-point type. Not all targets support
+all types however.
+
+::
+
+      declare float     @llvm.minnan.f32(float %Val0, float %Val1)
+      declare double    @llvm.minnan.f64(double %Val0, double %Val1)
+      declare x86_fp80  @llvm.minnan.f80(x86_fp80 %Val0, x86_fp80 %Val1)
+      declare fp128     @llvm.minnan.f128(fp128 %Val0, fp128 %Val1)
+      declare ppc_fp128 @llvm.minnan.ppcf128(ppc_fp128 %Val0, ppc_fp128 %Val1)
+
+Overview:
+"""""""""
+
+The '``llvm.minnan.*``' intrinsics return the minimum of the two
+arguments, propagating NaNs.
+
+
+Arguments:
+""""""""""
+
+The arguments and return value are floating-point numbers of the same
+type.
+
+Semantics:
+""""""""""
+If either operand is a NaN, returns NaN. If the operands compare
+equal, returns a value that compares equal to both operands. This
+means that llvm.minnan(+/-0.0, +/-0.0) could return either -0.0 or
+0.0. Note that this is different from IEEE 754-2018 semantics, which
+require that -0 compare less than +0 for this operation.
+
+'``llvm.maxnan.*``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+This is an overloaded intrinsic. You can use ``llvm.maxnan`` on any
+floating-point or vector of floating-point type. Not all targets support
+all types however.
+
+::
+
+      declare float     @llvm.maxnan.f32(float  %Val0, float  %Val1l)
+      declare double    @llvm.maxnan.f64(double %Val0, double %Val1)
+      declare x86_fp80  @llvm.maxnan.f80(x86_fp80  %Val0, x86_fp80  %Val1)
+      declare fp128     @llvm.maxnan.f128(fp128 %Val0, fp128 %Val1)
+      declare ppc_fp128 @llvm.maxnan.ppcf128(ppc_fp128  %Val0, ppc_fp128  %Val1)
+
+Overview:
+"""""""""
+
+The '``llvm.maxnan.*``' intrinsics return the maximum of the two
+arguments, propagating NaNs.
+
+
+Arguments:
+""""""""""
+
+The arguments and return value are floating-point numbers of the same
+type.
+
+Semantics:
+""""""""""
+If either operand is a NaN, returns NaN. If the operands compare
+equal, returns a value that compares equal to both operands. This
+means that llvm.maxnan(+/-0.0, +/-0.0) could return either -0.0 or
+0.0.Note that this is different from IEEE 754-2018 semantics, which
+require that -0 compare less than +0 for this operation.
+
 '``llvm.copysign.*``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 
 This is an overloaded intrinsic. You can use ``llvm.copysign`` on any
 floating-point or vector of floating-point type. Not all targets support

include/llvm/ADT/APFloat.h

 inline APFloat maxnum(const APFloat &A, const APFloat &B) {
   if (A.isNaN())
     return B;
   if (B.isNaN())
     return A;
   return (A.compare(B) == APFloat::cmpLessThan) ? B : A;
 }
 
+/// Returns the smaller of the 2 arguments if both are not Nan. If either
+/// argument is a NaN, return the NaN. Implements IEEE 754-2018 `minimum`
+/// semantics, except that -0 does not necessarily compare less than +0.
+LLVM_READONLY
+inline APFloat minnan(const APFloat &A, const APFloat &B) {
+  if (A.isNaN())
+    return A;
+  if (B.isNaN())
+    return B;
+  return (B.compare(A) == APFloat::cmpLessThan) ? B : A;
+}
+
+/// Returns the larger of the 2 arguments if both are not Nan. If either
+/// argument is a NaN, return the NaN. Implements IEEE 754-2018 `maximum`
+/// semantics, except that -0 does not necessarily compare less than +0.
+LLVM_READONLY
+inline APFloat maxnan(const APFloat &A, const APFloat &B) {
+  if (A.isNaN())
+    return A;
+  if (B.isNaN())
+    return B;
+  return (A.compare(B) == APFloat::cmpLessThan) ? B : A;
+}
+
 } // namespace llvm
 
 #undef APFLOAT_DISPATCH_ON_SEMANTICS
 #endif // LLVM_ADT_APFLOAT_H

include/llvm/IR/IRBuilder.h

CallInst *CreateMinNum(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateBinaryIntrinsic(Intrinsic::minnum, LHS, RHS, Name);
   }
 
   /// Create call to the maxnum intrinsic.
   CallInst *CreateMaxNum(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateBinaryIntrinsic(Intrinsic::maxnum, LHS, RHS, Name);
   }
 
+  /// Create call to the minnan intrinsic.
+  CallInst *CreateMinNan(Value *LHS, Value *RHS, const Twine &Name = "") {
+    return CreateBinaryIntrinsic(Intrinsic::minnan, LHS, RHS, Name);
+  }
+
+  /// Create call to the maxnan intrinsic.
+  CallInst *CreateMaxNan(Value *LHS, Value *RHS, const Twine &Name = "") {
+    return CreateBinaryIntrinsic(Intrinsic::maxnan, LHS, RHS, Name);
+  }
+
 private:
   /// Create a call to a masked intrinsic with given Id.
   CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops,
                                   ArrayRef<Type *> OverloadedTypes,
                                   const Twine &Name = "");
 
   Value *getCastedInt8PtrValue(Value *Ptr);
 };

include/llvm/IR/Intrinsics.td

 def int_minnum : Intrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, Commutative]
 >;
 def int_maxnum : Intrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, Commutative]
 >;
+def int_minnan : Intrinsic<[llvm_anyfloat_ty],
+  [LLVMMatchType<0>, LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable, Commutative]
+>;
+def int_maxnan : Intrinsic<[llvm_anyfloat_ty],
+  [LLVMMatchType<0>, LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable, Commutative]
+>;
 
 // NOTE: these are internal interfaces.
 def int_setjmp     : Intrinsic<[llvm_i32_ty],  [llvm_ptr_ty]>;
 def int_longjmp    : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoReturn]>;
 def int_sigsetjmp  : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;
 def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoReturn]>;
 
 // Internal interface for object size checking

lib/Analysis/ConstantFolding.cpp

 
 bool llvm::canConstantFoldCallTo(ImmutableCallSite CS, const Function *F) {
   if (CS.isNoBuiltin() || CS.isStrictFP())
     return false;
   switch (F->getIntrinsicID()) {
   case Intrinsic::fabs:
   case Intrinsic::minnum:
   case Intrinsic::maxnum:
+  case Intrinsic::minnan:
+  case Intrinsic::maxnan:
   case Intrinsic::log:
   case Intrinsic::log2:
   case Intrinsic::log10:
   case Intrinsic::exp:
   case Intrinsic::exp2:
   case Intrinsic::floor:
   case Intrinsic::ceil:
   case Intrinsic::sqrt:
if (auto *Op1 = dyn_cast<ConstantFP>(Operands[0])) {
         }
 
         if (IntrinsicID == Intrinsic::maxnum) {
           const APFloat &C1 = Op1->getValueAPF();
           const APFloat &C2 = Op2->getValueAPF();
           return ConstantFP::get(Ty->getContext(), maxnum(C1, C2));
         }
 
+        if (IntrinsicID == Intrinsic::minnan) {
+          const APFloat &C1 = Op1->getValueAPF();
+          const APFloat &C2 = Op2->getValueAPF();
+          return ConstantFP::get(Ty->getContext(), minnan(C1, C2));
+        }
+
+        if (IntrinsicID == Intrinsic::maxnan) {
+          const APFloat &C1 = Op1->getValueAPF();
+          const APFloat &C2 = Op2->getValueAPF();
+          return ConstantFP::get(Ty->getContext(), maxnan(C1, C2));
+        }
+
         if (!TLI)
           return nullptr;
         if ((Name == "pow" && TLI->has(LibFunc_pow)) ||
             (Name == "powf" && TLI->has(LibFunc_powf)) ||
             (Name == "__pow_finite" && TLI->has(LibFunc_pow_finite)) ||
             (Name == "__powf_finite" && TLI->has(LibFunc_powf_finite)))
           return ConstantFoldBinaryFP(pow, Op1V, Op2V, Ty);
         if ((Name == "fmod" && TLI->has(LibFunc_fmod)) ||

lib/Analysis/InstructionSimplify.cpp

if (auto *Power = dyn_cast<ConstantInt>(Op1)) {
       if (Power->isZero())
         return ConstantFP::get(Op0->getType(), 1.0);
       // powi(x, 1) -> x
       if (Power->isOne())
         return Op0;
     }
     break;
   case Intrinsic::maxnum:
-  case Intrinsic::minnum: {
+  case Intrinsic::minnum:
+  case Intrinsic::maxnan:
+  case Intrinsic::minnan: {
     // If the arguments are the same, this is a no-op.
     if (Op0 == Op1) return Op0;
 
-    // If one argument is NaN or undef, return the other argument.
-    if (match(Op0, m_CombineOr(m_NaN(), m_Undef()))) return Op1;
-    if (match(Op1, m_CombineOr(m_NaN(), m_Undef()))) return Op0;
+    // If one argument is undef, return the other argument.
+    if (match(Op0, m_Undef()))
+      return Op1;
+    if (match(Op1, m_Undef()))
+      return Op0;
+
+    // If one argument is NaN, return other or NaN appropriately.
+    bool PropagateNaN = (IID == Intrinsic::minnan || IID == Intrinsic::maxnan);
+    if (match(Op0, m_NaN()))
+      return PropagateNaN ? Op0 : Op1;
+    if (match(Op1, m_NaN()))
+      return PropagateNaN ? Op1 : Op0;
 
     // Min/max of the same operation with common operand:
     // m(m(X, Y)), X --> m(X, Y) (4 commuted variants)
     if (auto *M0 = dyn_cast<IntrinsicInst>(Op0))
       if (M0->getIntrinsicID() == IID &&
           (M0->getOperand(0) == Op1 || M0->getOperand(1) == Op1))
         return Op0;
     if (auto *M1 = dyn_cast<IntrinsicInst>(Op1))
       if (M1->getIntrinsicID() == IID &&
           (M1->getOperand(0) == Op0 || M1->getOperand(1) == Op0))
         return Op1;
 
-    // minnum(X, -Inf) --> -Inf (and commuted variant)
-    // maxnum(X, +Inf) --> +Inf (and commuted variant)
-    bool UseNegInf = IID == Intrinsic::minnum;
+    // min(X, -Inf) --> -Inf (and commuted variant)
+    // max(X, +Inf) --> +Inf (and commuted variant)
+    bool UseNegInf = (IID == Intrinsic::minnum || IID == Intrinsic::minnan);
     const APFloat *C;
     if ((match(Op0, m_APFloat(C)) && C->isInfinity() &&
          C->isNegative() == UseNegInf) ||
         (match(Op1, m_APFloat(C)) && C->isInfinity() &&
          C->isNegative() == UseNegInf))
       return ConstantFP::getInfinity(ReturnType, UseNegInf);
 
     // TODO: minnum(nnan x, inf) -> x

lib/Analysis/ValueTracking.cpp

case Instruction::Call:
     case Intrinsic::maxnum:
       return (isKnownNeverNaN(I->getOperand(0), TLI) &&
               cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI,
                                               SignBitOnly, Depth + 1)) ||
             (isKnownNeverNaN(I->getOperand(1), TLI) &&
               cannotBeOrderedLessThanZeroImpl(I->getOperand(1), TLI,
                                               SignBitOnly, Depth + 1));
 
+    case Intrinsic::maxnan:
+      return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
+                                             Depth + 1) ||
+             cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
+                                             Depth + 1);
     case Intrinsic::minnum:
+    case Intrinsic::minnan:
       return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
                                              Depth + 1) &&
              cannotBeOrderedLessThanZeroImpl(I->getOperand(1), TLI, SignBitOnly,
                                              Depth + 1);
     case Intrinsic::exp:
     case Intrinsic::exp2:
     case Intrinsic::fabs:
       return true;

lib/Analysis/VectorUtils.cpp

bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
   case Intrinsic::exp:
   case Intrinsic::exp2:
   case Intrinsic::log:
   case Intrinsic::log10:
   case Intrinsic::log2:
   case Intrinsic::fabs:
   case Intrinsic::minnum:
   case Intrinsic::maxnum:
+  case Intrinsic::minnan:
+  case Intrinsic::maxnan:
   case Intrinsic::copysign:
   case Intrinsic::floor:
   case Intrinsic::ceil:
   case Intrinsic::trunc:
   case Intrinsic::rint:
   case Intrinsic::nearbyint:
   case Intrinsic::round:
   case Intrinsic::bswap:

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitFP_EXTEND(SDNode *N);
     SDValue visitFNEG(SDNode *N);
     SDValue visitFABS(SDNode *N);
     SDValue visitFCEIL(SDNode *N);
     SDValue visitFTRUNC(SDNode *N);
     SDValue visitFFLOOR(SDNode *N);
     SDValue visitFMINNUM(SDNode *N);
     SDValue visitFMAXNUM(SDNode *N);
+    SDValue visitFMINNAN(SDNode *N);
+    SDValue visitFMAXNAN(SDNode *N);
     SDValue visitBRCOND(SDNode *N);
     SDValue visitBR_CC(SDNode *N);
     SDValue visitLOAD(SDNode *N);
 
     SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
     SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
 
     SDValue visitSTORE(SDNode *N);
SDValue DAGCombiner::visit(SDNode *N) {
   case ISD::FP_ROUND:           return visitFP_ROUND(N);
   case ISD::FP_ROUND_INREG:     return visitFP_ROUND_INREG(N);
   case ISD::FP_EXTEND:          return visitFP_EXTEND(N);
   case ISD::FNEG:               return visitFNEG(N);
   case ISD::FABS:               return visitFABS(N);
   case ISD::FFLOOR:             return visitFFLOOR(N);
   case ISD::FMINNUM:            return visitFMINNUM(N);
   case ISD::FMAXNUM:            return visitFMAXNUM(N);
+  case ISD::FMINNAN:            return visitFMINNAN(N);
+  case ISD::FMAXNAN:            return visitFMAXNAN(N);
   case ISD::FCEIL:              return visitFCEIL(N);
   case ISD::FTRUNC:             return visitFTRUNC(N);
   case ISD::BRCOND:             return visitBRCOND(N);
   case ISD::BR_CC:              return visitBR_CC(N);
   case ISD::LOAD:               return visitLOAD(N);
   case ISD::STORE:              return visitSTORE(N);
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
if (CFP1) {
             DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)),
             N0->getFlags());
     }
   }
 
   return SDValue();
 }
 
-SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
+static SDValue visitFMinMax(SelectionDAG &DAG, SDNode *N,
+                            APFloat (*Op)(const APFloat&, const APFloat&)) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
   const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
   const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
 
   if (N0CFP && N1CFP) {
     const APFloat &C0 = N0CFP->getValueAPF();
     const APFloat &C1 = N1CFP->getValueAPF();
-    return DAG.getConstantFP(minnum(C0, C1), SDLoc(N), VT);
+    return DAG.getConstantFP(Op(C0, C1), SDLoc(N), VT);
   }
 
   // Canonicalize to constant on RHS.
   if (isConstantFPBuildVectorOrConstantFP(N0) &&
      !isConstantFPBuildVectorOrConstantFP(N1))
-    return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
+    return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
 
   return SDValue();
 }
 
-SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
-  SDValue N0 = N->getOperand(0);
-  SDValue N1 = N->getOperand(1);
-  EVT VT = N->getValueType(0);
-  const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
-  const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
+SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
+  return visitFMinMax(DAG, N, minnum);
+}
 
-  if (N0CFP && N1CFP) {
-    const APFloat &C0 = N0CFP->getValueAPF();
-    const APFloat &C1 = N1CFP->getValueAPF();
-    return DAG.getConstantFP(maxnum(C0, C1), SDLoc(N), VT);
-  }
+SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
+  return visitFMinMax(DAG, N, maxnum);
 
-  // Canonicalize to constant on RHS.
-  if (isConstantFPBuildVectorOrConstantFP(N0) &&
-     !isConstantFPBuildVectorOrConstantFP(N1))
-    return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
+SDValue DAGCombiner::visitFMINNAN(SDNode *N) {
+  return visitFMinMax(DAG, N, minnan);
+}
 
-  return SDValue();
+SDValue DAGCombiner::visitFMAXNAN(SDNode *N) {
+  return visitFMinMax(DAG, N, maxnan);
 }
 
 SDValue DAGCombiner::visitFABS(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // fold (fabs c1) -> fabs(c1)
   if (isConstantFPBuildVectorOrConstantFP(N0))
auto ScaleShuffleMask = [](ArrayRef<int> Mask, int Scale) {
         return SmallVector<int, 8>(Mask.begin(), Mask.end());
 
       SmallVector<int, 8> NewMask;
       for (int M : Mask)
         for (int s = 0; s != Scale; ++s)
           NewMask.push_back(M < 0 ? -1 : Scale * M + s);
       return NewMask;
     };
-    
     SDValue BC0 = peekThroughOneUseBitcasts(N0);
     if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
       EVT SVT = VT.getScalarType();
       EVT InnerVT = BC0->getValueType(0);
       EVT InnerSVT = InnerVT.getScalarType();
 
       // Determine which shuffle works with the smaller scalar type.
       EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT;

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

unsigned Opc =
         I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)
             ? ISD::FMAXNAN
             : ISD::FMAXNUM;
     setValue(&I, DAG.getNode(Opc, sdl, VT,
                              getValue(I.getArgOperand(0)),
                              getValue(I.getArgOperand(1))));
     return nullptr;
   }
+  case Intrinsic::minnan:
+    setValue(&I, DAG.getNode(ISD::FMINNAN, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
+  case Intrinsic::maxnan:
+    setValue(&I, DAG.getNode(ISD::FMAXNAN, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
   case Intrinsic::copysign:
     setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
                              getValue(I.getArgOperand(0)).getValueType(),
                              getValue(I.getArgOperand(0)),
                              getValue(I.getArgOperand(1))));
     return nullptr;
   case Intrinsic::fma:
     setValue(&I, DAG.getNode(ISD::FMA, sdl,

lib/Transforms/InstCombine/InstCombineCalls.cpp

case Intrinsic::ssub_with_overflow: {
     if (OptimizeOverflowCheck(OCF, II->getArgOperand(0), II->getArgOperand(1),
                               *II, OperationResult, OverflowResult))
       return CreateOverflowTuple(II, OperationResult, OverflowResult);
 
     break;
   }
 
   case Intrinsic::minnum:
-  case Intrinsic::maxnum: {
+  case Intrinsic::maxnum:
+  case Intrinsic::minnan:
+  case Intrinsic::maxnan: {
     Value *Arg0 = II->getArgOperand(0);
     Value *Arg1 = II->getArgOperand(1);
     // Canonicalize constants to the RHS.
     if (isa<ConstantFP>(Arg0) && !isa<ConstantFP>(Arg1)) {
       II->setArgOperand(0, Arg1);
       II->setArgOperand(1, Arg0);
       return II;
     }
 
     Value *X, *Y;
     if (match(Arg0, m_FNeg(m_Value(X))) && match(Arg1, m_FNeg(m_Value(Y))) &&
         (Arg0->hasOneUse() || Arg1->hasOneUse())) {
       // If both operands are negated, invert the call and negate the result:
-      // minnum(-X, -Y) --> -(maxnum(X, Y))
-      // maxnum(-X, -Y) --> -(minnum(X, Y))
-      Intrinsic::ID NewIID = II->getIntrinsicID() == Intrinsic::maxnum ?
-          Intrinsic::minnum : Intrinsic::maxnum;
+      // min(-X, -Y) --> -(max(X, Y))
+      // max(-X, -Y) --> -(min(X, Y))
+      Intrinsic::ID NewIID;
+      switch (II->getIntrinsicID()) {
+      case Intrinsic::maxnum:
+        NewIID = Intrinsic::minnum;
+        break;
+      case Intrinsic::minnum:
+        NewIID = Intrinsic::maxnum;
+        break;
+      case Intrinsic::maxnan:
+        NewIID = Intrinsic::minnan;
+        break;
+      case Intrinsic::minnan:
+        NewIID = Intrinsic::maxnan;
+        break;
+      default:
+        llvm_unreachable("unexpected intrinsic ID");
+      }
       Value *NewCall = Builder.CreateIntrinsic(NewIID, { X, Y }, II);
       Instruction *FNeg = BinaryOperator::CreateFNeg(NewCall);
       FNeg->copyIRFlags(II);
       return FNeg;
     }
     break;
   }
   case Intrinsic::fmuladd: {

test/Analysis/ConstantFolding/min-max.ll

+; RUN: opt -instcombine -S -o - %s | FileCheck %s
+; Tests that constant folding of min and max operations works as expected.
+
+declare float @llvm.minnum.f32(float, float)
+declare float @llvm.maxnum.f32(float, float)
+declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
+
+declare float @llvm.minnan.f32(float, float)
+declare float @llvm.maxnan.f32(float, float)
+declare <4 x float> @llvm.minnan.v4f32(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.maxnan.v4f32(<4 x float>, <4 x float>)
+
+; CHECK: define float @minnum_float() {
+define float @minnum_float() {
+  ; CHECK-NEXT: ret float 5.000000e+00
+  %1 = call float @llvm.minnum.f32(float 5.0, float 42.0)
+  ret float %1
+}
+
+; CHECK: define <4 x float> @minnum_float_vec() {
+define <4 x float> @minnum_float_vec() {
+  ; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00,
+  ; CHECK-SAME:                  float 4.200000e+01, float 5.000000e+00>
+  %1 = call <4 x float> @llvm.minnum.v4f32(
+    <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>,
+    <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>
+  )
+  ret <4 x float> %1
+}
+
+; CHECK: define float @maxnum_float() {
+define float @maxnum_float() {
+  ; CHECK-NEXT: ret float 4.200000e+01
+  %1 = call float @llvm.maxnum.f32(float 5.0, float 42.0)
+  ret float %1
+}
+
+; CHECK: define <4 x float> @maxnum_float_vec() {
+define <4 x float> @maxnum_float_vec() {
+  ; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00,
+  ; CHECK-SAME:                  float 4.200000e+01, float 4.200000e+01>
+  %1 = call <4 x float> @llvm.maxnum.v4f32(
+    <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>,
+    <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>
+  )
+  ret <4 x float> %1
+}
+
+; CHECK: define float @minnan_float() {
+define float @minnan_float() {
+  ; CHECK-NEXT: ret float 5.000000e+00
+  %1 = call float @llvm.minnan.f32(float 5.0, float 42.0)
+  ret float %1
+}
+
+; CHECK: define <4 x float> @minnan_float_vec() {
+define <4 x float> @minnan_float_vec() {
+  ; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000,
+  ; CHECK-SAME:                  float 0x7FF8000000000000, float 5.000000e+00>
+  %1 = call <4 x float> @llvm.minnan.v4f32(
+    <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>,
+    <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>
+  )
+  ret <4 x float> %1
+}
+
+; CHECK: define float @maxnan_float() {
+define float @maxnan_float() {
+  ; CHECK-NEXT: ret float 4.200000e+01
+  %1 = call float @llvm.maxnan.f32(float 5.0, float 42.0)
+  ret float %1
+}
+
+; CHECK: define <4 x float> @maxnan_float_vec() {
+define <4 x float> @maxnan_float_vec() {
+  ; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000,
+  ; CHECK-SAME:                  float 0x7FF8000000000000, float 4.200000e+01>
+  %1 = call <4 x float> @llvm.maxnan.v4f32(
+    <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>,
+    <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>
+  )
+  ret <4 x float> %1
+}

test/Transforms/InstCombine/maxnan.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare float @llvm.maxnan.f32(float, float)
+declare <2 x float> @llvm.maxnan.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.maxnan.v4f32(<4 x float>, <4 x float>)
+
+declare double @llvm.maxnan.f64(double, double)
+declare <2 x double> @llvm.maxnan.v2f64(<2 x double>, <2 x double>)
+
+define float @constant_fold_maxnan_f32() {
+; CHECK-LABEL: @constant_fold_maxnan_f32(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float 1.0, float 2.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_inv() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_inv(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float 2.0, float 1.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_nan0() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_nan0(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.maxnan.f32(float 0x7FF8000000000000, float 2.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_nan1() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_nan1(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.maxnan.f32(float 2.0, float 0x7FF8000000000000)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_nan_nan() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_nan_nan(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.maxnan.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_p0_p0() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_p0_p0(
+; CHECK-NEXT:    ret float 0.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float 0.0, float 0.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_p0_n0() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_p0_n0(
+; CHECK-NEXT:    ret float 0.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float 0.0, float -0.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_n0_p0() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_n0_p0(
+; CHECK-NEXT:    ret float -0.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float -0.0, float 0.0)
+  ret float %x
+}
+
+define float @constant_fold_maxnan_f32_n0_n0() {
+; CHECK-LABEL: @constant_fold_maxnan_f32_n0_n0(
+; CHECK-NEXT:    ret float -0.000000e+00
+;
+  %x = call float @llvm.maxnan.f32(float -0.0, float -0.0)
+  ret float %x
+}
+
+define <4 x float> @constant_fold_maxnan_v4f32() {
+; CHECK-LABEL: @constant_fold_maxnan_v4f32(
+; CHECK-NEXT:    ret <4 x float> <float 2.000000e+00, float 8.000000e+00, float 1.000000e+01, float 9.000000e+00>
+;
+  %x = call <4 x float> @llvm.maxnan.v4f32(<4 x float> <float 1.0, float 8.0, float 3.0, float 9.0>, <4 x float> <float 2.0, float 2.0, float 10.0, float 5.0>)
+  ret <4 x float> %x
+}
+
+define double @constant_fold_maxnan_f64() {
+; CHECK-LABEL: @constant_fold_maxnan_f64(
+; CHECK-NEXT:    ret double 2.000000e+00
+;
+  %x = call double @llvm.maxnan.f64(double 1.0, double 2.0)
+  ret double %x
+}
+
+define double @constant_fold_maxnan_f64_nan0() {
+; CHECK-LABEL: @constant_fold_maxnan_f64_nan0(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.maxnan.f64(double 0x7FF8000000000000, double 2.0)
+  ret double %x
+}
+
+define double @constant_fold_maxnan_f64_nan1() {
+; CHECK-LABEL: @constant_fold_maxnan_f64_nan1(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.maxnan.f64(double 2.0, double 0x7FF8000000000000)
+  ret double %x
+}
+
+define double @constant_fold_maxnan_f64_nan_nan() {
+; CHECK-LABEL: @constant_fold_maxnan_f64_nan_nan(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.maxnan.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
+  ret double %x
+}
+
+define float @canonicalize_constant_maxnan_f32(float %x) {
+; CHECK-LABEL: @canonicalize_constant_maxnan_f32(
+; CHECK-NEXT:    [[Y:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT:    ret float [[Y]]
+;
+  %y = call float @llvm.maxnan.f32(float 1.0, float %x)
+  ret float %y
+}
+
+define float @maxnan_f32_nan_val(float %x) {
+; CHECK-LABEL: @maxnan_f32_nan_val(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %y = call float @llvm.maxnan.f32(float 0x7FF8000000000000, float %x)
+  ret float %y
+}
+
+define float @maxnan_f32_val_nan(float %x) {
+; CHECK-LABEL: @maxnan_f32_val_nan(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %y = call float @llvm.maxnan.f32(float %x, float 0x7FF8000000000000)
+  ret float %y
+}
+
+define float @maxnan4(float %x, float %y, float %z, float %w) {
+; CHECK-LABEL: @maxnan4(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.maxnan.f32(float [[Z:%.*]], float [[W:%.*]])
+; CHECK-NEXT:    [[C:%.*]] = call float @llvm.maxnan.f32(float [[A]], float [[B]])
+; CHECK-NEXT:    ret float [[C]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %z, float %w)
+  %c = call float @llvm.maxnan.f32(float %a, float %b)
+  ret float %c
+}
+
+; PR37404 - https://bugs.llvm.org/show_bug.cgi?id=37404
+
+define <2 x float> @neg_neg(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @neg_neg(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x float> @llvm.minnan.v2f32(<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, [[TMP1]]
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %negx = fsub <2 x float> <float -0.0, float -0.0>, %x
+  %negy = fsub <2 x float> <float -0.0, float -0.0>, %y
+  %r = call <2 x float> @llvm.maxnan.v2f32(<2 x float> %negx, <2 x float> %negy)
+  ret <2 x float> %r
+}
+
+; FMF is not required, but it should be propagated from the intrinsic (not the fnegs).
+
+define float @neg_neg_vec_fmf(float %x, float %y) {
+; CHECK-LABEL: @neg_neg_vec_fmf(
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub fast float -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %negx = fsub arcp float -0.0, %x
+  %negy = fsub afn float -0.0, %y
+  %r = call fast float @llvm.maxnan.f32(float %negx, float %negy)
+  ret float %r
+}
+
+; 1 extra use of an intermediate value should still allow the fold,
+; but 2 would require more instructions than we started with.
+
+declare void @use(float)
+define float @neg_neg_extra_use_x(float %x, float %y) {
+; CHECK-LABEL: @neg_neg_extra_use_x(
+; CHECK-NEXT:    [[NEGX:%.*]] = fsub float -0.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.minnan.f32(float [[X]], float [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub float -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    call void @use(float [[NEGX]])
+; CHECK-NEXT:    ret float [[R]]
+;
+  %negx = fsub float -0.0, %x
+  %negy = fsub float -0.0, %y
+  %r = call float @llvm.maxnan.f32(float %negx, float %negy)
+  call void @use(float %negx)
+  ret float %r
+}
+
+define float @neg_neg_extra_use_y(float %x, float %y) {
+; CHECK-LABEL: @neg_neg_extra_use_y(
+; CHECK-NEXT:    [[NEGY:%.*]] = fsub float -0.000000e+00, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y]])
+; CHECK-NEXT:    [[R:%.*]] = fsub float -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    call void @use(float [[NEGY]])
+; CHECK-NEXT:    ret float [[R]]
+;
+  %negx = fsub float -0.0, %x
+  %negy = fsub float -0.0, %y
+  %r = call float @llvm.maxnan.f32(float %negx, float %negy)
+  call void @use(float %negy)
+  ret float %r
+}
+
+define float @neg_neg_extra_use_x_and_y(float %x, float %y) {
+; CHECK-LABEL: @neg_neg_extra_use_x_and_y(
+; CHECK-NEXT:    [[NEGX:%.*]] = fsub float -0.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[NEGY:%.*]] = fsub float -0.000000e+00, [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = call float @llvm.maxnan.f32(float [[NEGX]], float [[NEGY]])
+; CHECK-NEXT:    call void @use(float [[NEGX]])
+; CHECK-NEXT:    call void @use(float [[NEGY]])
+; CHECK-NEXT:    ret float [[R]]
+;
+  %negx = fsub float -0.0, %x
+  %negy = fsub float -0.0, %y
+  %r = call float @llvm.maxnan.f32(float %negx, float %negy)
+  call void @use(float %negx)
+  call void @use(float %negy)
+  ret float %r
+}

test/Transforms/InstCombine/minnan.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare float @llvm.minnan.f32(float, float)
+declare float @llvm.minnan.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.minnan.v4f32(<4 x float>, <4 x float>)
+
+declare double @llvm.minnan.f64(double, double)
+declare <2 x double> @llvm.minnan.v2f64(<2 x double>, <2 x double>)
+
+declare float @llvm.maxnan.f32(float, float)
+
+define float @constant_fold_minnan_f32() {
+; CHECK-LABEL: @constant_fold_minnan_f32(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float 1.0, float 2.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_inv() {
+; CHECK-LABEL: @constant_fold_minnan_f32_inv(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float 2.0, float 1.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_nan0() {
+; CHECK-LABEL: @constant_fold_minnan_f32_nan0(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.minnan.f32(float 0x7FF8000000000000, float 2.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_nan1() {
+; CHECK-LABEL: @constant_fold_minnan_f32_nan1(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.minnan.f32(float 2.0, float 0x7FF8000000000000)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_nan_nan() {
+; CHECK-LABEL: @constant_fold_minnan_f32_nan_nan(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %x = call float @llvm.minnan.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_p0_p0() {
+; CHECK-LABEL: @constant_fold_minnan_f32_p0_p0(
+; CHECK-NEXT:    ret float 0.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float 0.0, float 0.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_p0_n0() {
+; CHECK-LABEL: @constant_fold_minnan_f32_p0_n0(
+; CHECK-NEXT:    ret float 0.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float 0.0, float -0.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_n0_p0() {
+; CHECK-LABEL: @constant_fold_minnan_f32_n0_p0(
+; CHECK-NEXT:    ret float -0.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float -0.0, float 0.0)
+  ret float %x
+}
+
+define float @constant_fold_minnan_f32_n0_n0() {
+; CHECK-LABEL: @constant_fold_minnan_f32_n0_n0(
+; CHECK-NEXT:    ret float -0.000000e+00
+;
+  %x = call float @llvm.minnan.f32(float -0.0, float -0.0)
+  ret float %x
+}
+
+define <4 x float> @constant_fold_minnan_v4f32() {
+; CHECK-LABEL: @constant_fold_minnan_v4f32(
+; CHECK-NEXT:    ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 5.000000e+00>
+;
+  %x = call <4 x float> @llvm.minnan.v4f32(<4 x float> <float 1.0, float 8.0, float 3.0, float 9.0>, <4 x float> <float 2.0, float 2.0, float 10.0, float 5.0>)
+  ret <4 x float> %x
+}
+
+define double @constant_fold_minnan_f64() {
+; CHECK-LABEL: @constant_fold_minnan_f64(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %x = call double @llvm.minnan.f64(double 1.0, double 2.0)
+  ret double %x
+}
+
+define double @constant_fold_minnan_f64_nan0() {
+; CHECK-LABEL: @constant_fold_minnan_f64_nan0(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.minnan.f64(double 0x7FF8000000000000, double 2.0)
+  ret double %x
+}
+
+define double @constant_fold_minnan_f64_nan1() {
+; CHECK-LABEL: @constant_fold_minnan_f64_nan1(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.minnan.f64(double 2.0, double 0x7FF8000000000000)
+  ret double %x
+}
+
+define double @constant_fold_minnan_f64_nan_nan() {
+; CHECK-LABEL: @constant_fold_minnan_f64_nan_nan(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %x = call double @llvm.minnan.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
+  ret double %x
+}
+
+define float @canonicalize_constant_minnan_f32(float %x) {
+; CHECK-LABEL: @canonicalize_constant_minnan_f32(
+; CHECK-NEXT:    [[Y:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT:    ret float [[Y]]
+;
+  %y = call float @llvm.minnan.f32(float 1.0, float %x)
+  ret float %y
+}
+
+define float @minnan_f32_nan_val(float %x) {
+; CHECK-LABEL: @minnan_f32_nan_val(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %y = call float @llvm.minnan.f32(float 0x7FF8000000000000, float %x)
+  ret float %y
+}
+
+define float @minnan_f32_val_nan(float %x) {
+; CHECK-LABEL: @minnan_f32_val_nan(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %y = call float @llvm.minnan.f32(float %x, float 0x7FF8000000000000)
+  ret float %y
+}
+
+define float @minnan4(float %x, float %y, float %z, float %w) {
+; CHECK-LABEL: @minnan4(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.minnan.f32(float [[Z:%.*]], float [[W:%.*]])
+; CHECK-NEXT:    [[C:%.*]] = call float @llvm.minnan.f32(float [[A]], float [[B]])
+; CHECK-NEXT:    ret float [[C]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %z, float %w)
+  %c = call float @llvm.minnan.f32(float %a, float %b)
+  ret float %c
+}
+
+define float @minnan_x_maxnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @minnan_x_maxnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.minnan.f32(float [[X]], float [[A]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %x, float %a)
+  ret float %b
+}
+
+define float @maxnan_x_minnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @maxnan_x_minnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.maxnan.f32(float [[X]], float [[A]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %x, float %a)
+  ret float %b
+}
+
+; PR37405 - https://bugs.llvm.org/show_bug.cgi?id=37405
+
+define double @neg_neg(double %x, double %y) {
+; CHECK-LABEL: @neg_neg(
+; CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.maxnan.f64(double [[X:%.*]], double [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub double -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    ret double [[R]]
+;
+  %negx = fsub double -0.0, %x
+  %negy = fsub double -0.0, %y
+  %r = call double @llvm.minnan.f64(double %negx, double %negy)
+  ret double %r
+}
+
+; FMF is not required, but it should be propagated from the intrinsic (not the fnegs).
+; Also, make sure this works with vectors.
+
+define <2 x double> @neg_neg_vec_fmf(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @neg_neg_vec_fmf(
+; CHECK-NEXT:    [[TMP1:%.*]] = call nnan ninf <2 x double> @llvm.maxnan.v2f64(<2 x double> [[X:%.*]], <2 x double> [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub nnan ninf <2 x double> <double -0.000000e+00, double -0.000000e+00>, [[TMP1]]
+; CHECK-NEXT:    ret <2 x double> [[R]]
+;
+  %negx = fsub reassoc <2 x double> <double -0.0, double -0.0>, %x
+  %negy = fsub fast <2 x double> <double -0.0, double -0.0>, %y
+  %r = call nnan ninf <2 x double> @llvm.minnan.v2f64(<2 x double> %negx, <2 x double> %negy)
+  ret <2 x double> %r
+}
+
+; 1 extra use of an intermediate value should still allow the fold,
+; but 2 would require more instructions than we started with.
+
+declare void @use(double)
+define double @neg_neg_extra_use_x(double %x, double %y) {
+; CHECK-LABEL: @neg_neg_extra_use_x(
+; CHECK-NEXT:    [[NEGX:%.*]] = fsub double -0.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.maxnan.f64(double [[X]], double [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = fsub double -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    call void @use(double [[NEGX]])
+; CHECK-NEXT:    ret double [[R]]
+;
+  %negx = fsub double -0.0, %x
+  %negy = fsub double -0.0, %y
+  %r = call double @llvm.minnan.f64(double %negx, double %negy)
+  call void @use(double %negx)
+  ret double %r
+}
+
+define double @neg_neg_extra_use_y(double %x, double %y) {
+; CHECK-LABEL: @neg_neg_extra_use_y(
+; CHECK-NEXT:    [[NEGY:%.*]] = fsub double -0.000000e+00, [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.maxnan.f64(double [[X:%.*]], double [[Y]])
+; CHECK-NEXT:    [[R:%.*]] = fsub double -0.000000e+00, [[TMP1]]
+; CHECK-NEXT:    call void @use(double [[NEGY]])
+; CHECK-NEXT:    ret double [[R]]
+;
+  %negx = fsub double -0.0, %x
+  %negy = fsub double -0.0, %y
+  %r = call double @llvm.minnan.f64(double %negx, double %negy)
+  call void @use(double %negy)
+  ret double %r
+}
+
+define double @neg_neg_extra_use_x_and_y(double %x, double %y) {
+; CHECK-LABEL: @neg_neg_extra_use_x_and_y(
+; CHECK-NEXT:    [[NEGX:%.*]] = fsub double -0.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[NEGY:%.*]] = fsub double -0.000000e+00, [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = call double @llvm.minnan.f64(double [[NEGX]], double [[NEGY]])
+; CHECK-NEXT:    call void @use(double [[NEGX]])
+; CHECK-NEXT:    call void @use(double [[NEGY]])
+; CHECK-NEXT:    ret double [[R]]
+;
+  %negx = fsub double -0.0, %x
+  %negy = fsub double -0.0, %y
+  %r = call double @llvm.minnan.f64(double %negx, double %negy)
+  call void @use(double %negx)
+  call void @use(double %negy)
+  ret double %r
+}

test/Transforms/InstSimplify/floating-point-arithmetic.ll

 ; CHECK-LABEL: @maxnum_neginf(
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.maxnum.f32(float 0xFFF0000000000000, float [[X:%.*]])
 ; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.maxnum.f32(float 0xFFF0000000000000, float %x)
   ret float %val
 }
 
+declare float @llvm.minnan.f32(float, float)
+declare float @llvm.maxnan.f32(float, float)
+declare double @llvm.minnan.f64(double, double)
+declare double @llvm.maxnan.f64(double, double)
+declare <2 x double> @llvm.minnan.v2f64(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.maxnan.v2f64(<2 x double>, <2 x double>)
+
+; From the LangRef for minnan/maxnan:
+; "If either operand is a NaN, returns NaN."
+
+define double @maxnan_nan_op0(double %x) {
+; CHECK-LABEL: @maxnan_nan_op0(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %r = call double @llvm.maxnan.f64(double 0x7ff8000000000000, double %x)
+  ret double %r
+}
+
+define double @maxnan_nan_op1(double %x) {
+; CHECK-LABEL: @maxnan_nan_op1(
+; CHECK-NEXT:    ret double 0x7FF800000000DEAD
+;
+  %r = call double @llvm.maxnan.f64(double %x, double 0x7ff800000000dead)
+  ret double %r
+}
+
+define double @minnan_nan_op0(double %x) {
+; CHECK-LABEL: @minnan_nan_op0(
+; CHECK-NEXT:    ret double 0x7FF8000DEAD00000
+;
+  %r = call double @llvm.minnan.f64(double 0x7ff8000dead00000, double %x)
+  ret double %r
+}
+
+define double @minnan_nan_op1(double %x) {
+; CHECK-LABEL: @minnan_nan_op1(
+; CHECK-NEXT:    ret double 0x7FF800DEAD00DEAD
+;
+  %r = call double @llvm.minnan.f64(double %x, double 0x7ff800dead00dead)
+  ret double %r
+}
+
+define <2 x double> @maxnan_nan_op0_vec(<2 x double> %x) {
+; CHECK-LABEL: @maxnan_nan_op0_vec(
+; CHECK-NEXT:    ret <2 x double> <double 0x7FF8000000000000, double undef>
+;
+  %r = call <2 x double> @llvm.maxnan.v2f64(<2 x double> <double 0x7ff8000000000000, double undef>, <2 x double> %x)
+  ret <2 x double> %r
+}
+
+define <2 x double> @maxnan_nan_op1_vec(<2 x double> %x) {
+; CHECK-LABEL: @maxnan_nan_op1_vec(
+; CHECK-NEXT:    ret <2 x double> <double 0x7FF800000000DEAD, double 0x7FF8FFFFFFFFFFFF>
+;
+  %r = call <2 x double> @llvm.maxnan.v2f64(<2 x double> %x, <2 x double> <double 0x7ff800000000dead, double 0x7ff8ffffffffffff>)
+  ret <2 x double> %r
+}
+
+define <2 x double> @minnan_nan_op0_vec(<2 x double> %x) {
+; CHECK-LABEL: @minnan_nan_op0_vec(
+; CHECK-NEXT:    ret <2 x double> <double undef, double 0x7FF8000DEAD00000>
+;
+  %r = call <2 x double> @llvm.minnan.v2f64(<2 x double> <double undef, double 0x7ff8000dead00000>, <2 x double> %x)
+  ret <2 x double> %r
+}
+
+define <2 x double> @minnan_nan_op1_vec(<2 x double> %x) {
+; CHECK-LABEL: @minnan_nan_op1_vec(
+; CHECK-NEXT:    ret <2 x double> <double 0x7FF800DEAD00DEAD, double 0x7FF800DEAD00DEAD>
+;
+  %r = call <2 x double> @llvm.minnan.v2f64(<2 x double> %x, <2 x double> <double 0x7ff800dead00dead, double 0x7ff800dead00dead>)
+  ret <2 x double> %r
+}
+
+define float @maxnan_undef_op1(float %x) {
+; CHECK-LABEL: @maxnan_undef_op1(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %val = call float @llvm.maxnan.f32(float %x, float undef)
+  ret float %val
+}
+
+define float @maxnan_undef_op0(float %x) {
+; CHECK-LABEL: @maxnan_undef_op0(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %val = call float @llvm.maxnan.f32(float undef, float %x)
+  ret float %val
+}
+
+define float @minnan_undef_op1(float %x) {
+; CHECK-LABEL: @minnan_undef_op1(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %val = call float @llvm.minnan.f32(float %x, float undef)
+  ret float %val
+}
+
+define float @minnan_undef_op0(float %x) {
+; CHECK-LABEL: @minnan_undef_op0(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %val = call float @llvm.minnan.f32(float undef, float %x)
+  ret float %val
+}
+
+define float @minnan_undef_undef(float %x) {
+; CHECK-LABEL: @minnan_undef_undef(
+; CHECK-NEXT:    ret float undef
+;
+  %val = call float @llvm.minnan.f32(float undef, float undef)
+  ret float %val
+}
+
+define float @maxnan_undef_undef(float %x) {
+; CHECK-LABEL: @maxnan_undef_undef(
+; CHECK-NEXT:    ret float undef
+;
+  %val = call float @llvm.maxnan.f32(float undef, float undef)
+  ret float %val
+}
+
+define float @minnan_same_args(float %x) {
+; CHECK-LABEL: @minnan_same_args(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %y = call float @llvm.minnan.f32(float %x, float %x)
+  ret float %y
+}
+
+define float @maxnan_same_args(float %x) {
+; CHECK-LABEL: @maxnan_same_args(
+; CHECK-NEXT:    ret float [[X:%.*]]
+;
+  %y = call float @llvm.maxnan.f32(float %x, float %x)
+  ret float %y
+}
+
+define float @minnan_x_minnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @minnan_x_minnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %x, float %a)
+  ret float %b
+}
+
+define float @minnan_y_minnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @minnan_y_minnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %y, float %a)
+  ret float %b
+}
+
+define float @minnan_x_y_minnan_x(float %x, float %y) {
+; CHECK-LABEL: @minnan_x_y_minnan_x(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %a, float %x)
+  ret float %b
+}
+
+define float @minnan_x_y_minnan_y(float %x, float %y) {
+; CHECK-LABEL: @minnan_x_y_minnan_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %a, float %y)
+  ret float %b
+}
+
+; negative test
+
+define float @minnan_z_minnan_x_y(float %x, float %y, float %z) {
+; CHECK-LABEL: @minnan_z_minnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.minnan.f32(float [[Z:%.*]], float [[A]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %z, float %a)
+  ret float %b
+}
+
+; negative test
+
+define float @minnan_x_y_minnan_z(float %x, float %y, float %z) {
+; CHECK-LABEL: @minnan_x_y_minnan_z(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.minnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.minnan.f32(float [[A]], float [[Z:%.*]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.minnan.f32(float %x, float %y)
+  %b = call float @llvm.minnan.f32(float %a, float %z)
+  ret float %b
+}
+
+; minnan(X, -INF) --> -INF
+
+define float @minnan_neginf(float %x) {
+; CHECK-LABEL: @minnan_neginf(
+; CHECK-NEXT:    ret float 0xFFF0000000000000
+;
+  %val = call float @llvm.minnan.f32(float %x, float 0xFFF0000000000000)
+  ret float %val
+}
+
+define <2 x double> @minnan_neginf_commute_vec(<2 x double> %x) {
+; CHECK-LABEL: @minnan_neginf_commute_vec(
+; CHECK-NEXT:    ret <2 x double> <double 0xFFF0000000000000, double 0xFFF0000000000000>
+;
+  %r = call <2 x double> @llvm.minnan.v2f64(<2 x double> <double 0xFFF0000000000000, double 0xFFF0000000000000>, <2 x double> %x)
+  ret <2 x double> %r
+}
+
+; negative test
+
+define float @minnan_inf(float %x) {
+; CHECK-LABEL: @minnan_inf(
+; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.minnan.f32(float 0x7FF0000000000000, float [[X:%.*]])
+; CHECK-NEXT:    ret float [[VAL]]
+;
+  %val = call float @llvm.minnan.f32(float 0x7FF0000000000000, float %x)
+  ret float %val
+}
+define float @maxnan_x_maxnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @maxnan_x_maxnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %x, float %a)
+  ret float %b
+}
+
+define float @maxnan_y_maxnan_x_y(float %x, float %y) {
+; CHECK-LABEL: @maxnan_y_maxnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %y, float %a)
+  ret float %b
+}
+
+define float @maxnan_x_y_maxnan_x(float %x, float %y) {
+; CHECK-LABEL: @maxnan_x_y_maxnan_x(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %a, float %x)
+  ret float %b
+}
+
+define float @maxnan_x_y_maxnan_y(float %x, float %y) {
+; CHECK-LABEL: @maxnan_x_y_maxnan_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    ret float [[A]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %a, float %y)
+  ret float %b
+}
+
+; negative test
+
+define float @maxnan_z_maxnan_x_y(float %x, float %y, float %z) {
+; CHECK-LABEL: @maxnan_z_maxnan_x_y(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.maxnan.f32(float [[Z:%.*]], float [[A]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %z, float %a)
+  ret float %b
+}
+
+; negative test
+
+define float @maxnan_x_y_maxnan_z(float %x, float %y, float %z) {
+; CHECK-LABEL: @maxnan_x_y_maxnan_z(
+; CHECK-NEXT:    [[A:%.*]] = call float @llvm.maxnan.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT:    [[B:%.*]] = call float @llvm.maxnan.f32(float [[A]], float [[Z:%.*]])
+; CHECK-NEXT:    ret float [[B]]
+;
+  %a = call float @llvm.maxnan.f32(float %x, float %y)
+  %b = call float @llvm.maxnan.f32(float %a, float %z)
+  ret float %b
+}
+
+; maxnan(X, INF) --> INF
+
+define <2 x double> @maxnan_inf(<2 x double> %x) {
+; CHECK-LABEL: @maxnan_inf(
+; CHECK-NEXT:    ret <2 x double> <double 0x7FF0000000000000, double 0x7FF0000000000000>
+;
+  %val = call <2 x double> @llvm.maxnan.v2f64(<2 x double> %x, <2 x double><double 0x7FF0000000000000, double 0x7FF0000000000000>)
+  ret <2 x double> %val
+}
+
+define float @maxnan_inf_commute(float %x) {
+; CHECK-LABEL: @maxnan_inf_commute(
+; CHECK-NEXT:    ret float 0x7FF0000000000000
+;
+  %val = call float @llvm.maxnan.f32(float 0x7FF0000000000000, float %x)
+  ret float %val
+}
+
 ; Y - (Y - X) --> X
 
 define float @fsub_fsub_common_op(float %x, float %y) {
 ; CHECK-LABEL: @fsub_fsub_common_op(
 ; CHECK-NEXT:    ret float [[X:%.*]]
 ;
   %s = fsub float %y, %x
   %r = fsub reassoc nsz float %y, %s

test/Transforms/InstSimplify/floating-point-compare.ll

 declare double @llvm.fabs.f64(double)
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
 declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
 declare float @llvm.sqrt.f32(float)
 declare double @llvm.powi.f64(double,i32)
 declare float @llvm.exp.f32(float)
 declare float @llvm.minnum.f32(float, float)
 declare float @llvm.maxnum.f32(float, float)
+declare float @llvm.maxnan.f32(float, float)
 declare double @llvm.exp2.f64(double)
 declare float @llvm.fma.f32(float,float,float)
 
 declare void @expect_equal(i1,i1)
 
 define i1 @orderedLessZeroTree(float,float,float,float) {
 ; CHECK-LABEL: @orderedLessZeroTree(
 ; CHECK-NEXT:    ret i1 true

 ; CHECK-NEXT:    ret i1 [[UGE]]
 ;
   %a = call float @llvm.exp.f32(float %0)
   %b = call float @llvm.maxnum.f32(float %a, float %1)
   %uge = fcmp uge float %b, 0.000000e+00
   ret i1 %uge
 }
 
+; But using maxnan, we can simplify, since the NaN would be propagated
+
+define i1 @orderedLessZeroMaxNaN(float, float) {
+; CHECK-LABEL: @orderedLessZeroMaxNaN(
+; CHECK-NEXT:    ret i1 true
+;
+  %a = call float @llvm.exp.f32(float %0)
+  %b = call float @llvm.maxnan.f32(float %a, float %1)
+  %uge = fcmp uge float %b, 0.000000e+00
+  ret i1 %uge
+}
+
 define i1 @known_positive_olt_with_negative_constant(double %a) {
 ; CHECK-LABEL: @known_positive_olt_with_negative_constant(
 ; CHECK-NEXT:    ret i1 false
 ;
   %call = call double @llvm.fabs.f64(double %a)
   %cmp = fcmp olt double %call, -1.0
   ret i1 %cmp
 }

test/Transforms/LICM/hoist-round.ll

 ; RUN: opt -S -licm < %s | FileCheck %s
 ; RUN: opt -aa-pipeline=basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop(licm)' -S %s | FileCheck %s
 
 target datalayout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32"
 
 ; This test verifies that ceil, floor, nearbyint, trunc, rint, round,
-; copysign, minnum, maxnum and fabs intrinsics are considered safe
-; to speculate.
+; copysign, minnum, maxnum minnan, maxnan, and fabs intrinsics are
+; considered safe to speculate.
 
 ; CHECK-LABEL: @test
 ; CHECK: call float @llvm.ceil.f32
 ; CHECK: call float @llvm.floor.f32
 ; CHECK: call float @llvm.nearbyint.f32
 ; CHECK: call float @llvm.rint.f32
 ; CHECK: call float @llvm.round.f32
 ; CHECK: call float @llvm.trunc.f32
for.body:
   %tmp.3 = call float @llvm.nearbyint.f32(float %tmp.2)
   %tmp.4 = call float @llvm.rint.f32(float %tmp.3)
   %tmp.5 = call float @llvm.round.f32(float %tmp.4)
   %tmp.6 = call float @llvm.trunc.f32(float %tmp.5)
   %tmp.7 = call float @llvm.fabs.f32(float %tmp.6)
   %tmp.8 = call float @llvm.copysign.f32(float %tmp.7, float %arg2)
   %tmp.9 = call float @llvm.minnum.f32(float %tmp.8, float %arg2)
   %tmp.10 = call float @llvm.maxnum.f32(float %tmp.9, float %arg2)
-  %tmp.11 = call float @llvm.powi.f32(float %tmp.10, i32 4)
-  call void @consume(float %tmp.11)
+  %tmp.11 = call float @llvm.minnan.f32(float %tmp.10, float %arg2)
+  %tmp.12 = call float @llvm.maxnan.f32(float %tmp.11, float %arg2)
+  %tmp.13 = call float @llvm.powi.f32(float %tmp.12, i32 4)
+  call void @consume(float %tmp.13)
   %IND.new = add i32 %IND, 1
   br label %for.head
 
 exit:
   ret void
 }
 
 declare void @consume(float)
 
 declare float @llvm.ceil.f32(float)
 declare float @llvm.floor.f32(float)
 declare float @llvm.nearbyint.f32(float)
 declare float @llvm.rint.f32(float)
 declare float @llvm.round.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.fabs.f32(float)
 declare float @llvm.copysign.f32(float, float)
 declare float @llvm.minnum.f32(float, float)
 declare float @llvm.maxnum.f32(float, float)
+declare float @llvm.minnan.f32(float, float)
+declare float @llvm.maxnan.f32(float, float)
 declare float @llvm.powi.f32(float, i32)

test/Transforms/LoopVectorize/intrinsic.ll

for.body:                                         ; preds = %entry, %for.body
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
+
+declare float @llvm.minnan.f32(float, float) nounwind readnone
+
+;CHECK-LABEL: @minnan_f32(
+;CHECK: llvm.minnan.v4f32
+;CHECK: ret void
+define void @minnan_f32(i32 %n, float* noalias %y, float* noalias %x, float* noalias %z) nounwind uwtable {
+entry:
+  %cmp9 = icmp sgt i32 %n, 0
+  br i1 %cmp9, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
+  %call = tail call float @llvm.minnan.f32(float %0, float %1) nounwind readnone
+  %arrayidx4 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx4, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+declare float @llvm.maxnan.f32(float, float) nounwind readnone
+
+;CHECK-LABEL: @maxnan_f32(
+;CHECK: llvm.maxnan.v4f32
+;CHECK: ret void
+define void @maxnan_f32(i32 %n, float* noalias %y, float* noalias %x, float* noalias %z) nounwind uwtable {
+entry:
+  %cmp9 = icmp sgt i32 %n, 0
+  br i1 %cmp9, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
+  %call = tail call float @llvm.maxnan.f32(float %0, float %1) nounwind readnone
+  %arrayidx4 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx4, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}

test/Transforms/Scalarizer/intrinsics.ll

 ; RUN: opt -S -scalarizer %s | FileCheck %s
 
 ; Unary fp
 declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
 
 ; Binary fp
 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
+declare <2 x float> @llvm.minnan.v2f32(<2 x float>, <2 x float>)
+declare <2 x float> @llvm.maxnan.v2f32(<2 x float>, <2 x float>)
 
 ; Ternary fp
 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
 
 ; Binary int
 declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)
 
 ; Unary int plus constant scalar operand

 ; CHECK: %minnum.upto0 = insertelement <2 x float> undef, float %minnum.i0, i32 0
 ; CHECK: %minnum = insertelement <2 x float> %minnum.upto0, float %minnum.i1, i32 1
 ; CHECK: ret <2 x float> %minnum
 define <2 x float> @scalarize_minnum_v2f32(<2 x float> %x, <2 x float> %y) #0 {
   %minnum = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y)
   ret <2 x float> %minnum
 }
 
+; CHECK-LABEL: @scalarize_minnan_v2f32(
+; CHECK: %minnan.i0 = call float @llvm.minnan.f32(float %x.i0, float %y.i0)
+; CHECK: %minnan.i1 = call float @llvm.minnan.f32(float %x.i1, float %y.i1)
+; CHECK: %minnan.upto0 = insertelement <2 x float> undef, float %minnan.i0, i32 0
+; CHECK: %minnan = insertelement <2 x float> %minnan.upto0, float %minnan.i1, i32 1
+; CHECK: ret <2 x float> %minnan
+define <2 x float> @scalarize_minnan_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+  %minnan = call <2 x float> @llvm.minnan.v2f32(<2 x float> %x, <2 x float> %y)
+  ret <2 x float> %minnan
+}
+
+; CHECK-LABEL: @scalarize_maxnan_v2f32(
+; CHECK: %maxnan.i0 = call float @llvm.maxnan.f32(float %x.i0, float %y.i0)
+; CHECK: %maxnan.i1 = call float @llvm.maxnan.f32(float %x.i1, float %y.i1)
+; CHECK: %maxnan.upto0 = insertelement <2 x float> undef, float %maxnan.i0, i32 0
+; CHECK: %maxnan = insertelement <2 x float> %maxnan.upto0, float %maxnan.i1, i32 1
+; CHECK: ret <2 x float> %maxnan
+define <2 x float> @scalarize_maxnan_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+  %maxnan = call <2 x float> @llvm.maxnan.v2f32(<2 x float> %x, <2 x float> %y)
+  ret <2 x float> %maxnan
+}
+
 ; CHECK-LABEL: @scalarize_fma_v2f32(
 ; CHECK: %fma.i0 = call float @llvm.fma.f32(float %x.i0, float %y.i0, float %z.i0)
 ; CHECK: %fma.i1 = call float @llvm.fma.f32(float %x.i1, float %y.i1, float %z.i1)
 ; CHECK: %fma.upto0 = insertelement <2 x float> undef, float %fma.i0, i32 0
 ; CHECK: %fma = insertelement <2 x float> %fma.upto0, float %fma.i1, i32 1
 ; CHECK: ret <2 x float> %fma
 define <2 x float> @scalarize_fma_v2f32(<2 x float> %x, <2 x float> %y, <2 x float> %z) #0 {
   %fma = call <2 x float> @llvm.fma.v2f32(<2 x float> %x, <2 x float> %y, <2 x float> %z)

test/Transforms/SimplifyCFG/speculate-math.ll

 ; RUN: opt -S -simplifycfg < %s | FileCheck %s --check-prefix=EXPENSIVE --check-prefix=ALL
 ; RUN: opt -S -simplifycfg -speculate-one-expensive-inst=false < %s | FileCheck %s --check-prefix=CHEAP --check-prefix=ALL
 
 declare float @llvm.sqrt.f32(float) nounwind readonly
 declare float @llvm.fma.f32(float, float, float) nounwind readonly
 declare float @llvm.fmuladd.f32(float, float, float) nounwind readonly
 declare float @llvm.fabs.f32(float) nounwind readonly
 declare float @llvm.minnum.f32(float, float) nounwind readonly
 declare float @llvm.maxnum.f32(float, float) nounwind readonly
+declare float @llvm.minnan.f32(float, float) nounwind readonly
+declare float @llvm.maxnan.f32(float, float) nounwind readonly
 
 ; ALL-LABEL: @fdiv_test(
 ; EXPENSIVE: select i1 %cmp, double %div, double 0.0
 ; CHEAP-NOT: select
 
 define double @fdiv_test(double %a, double %b) {
 entry:
   %cmp = fcmp ogt double %a, 0.0
cond.else.i:                                      ; preds = %entry
   %0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
   br label %test_maxnum.exit
 
 test_maxnum.exit:                                   ; preds = %cond.else.i, %entry
   %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
   store float %cond.i, float addrspace(1)* %out, align 4
   ret void
 }
+
+; ALL-LABEL: @minnan_test(
+; ALL: select
+define void @minnan_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+entry:
+  %cmp.i = fcmp olt float %a, 0.000000e+00
+  br i1 %cmp.i, label %test_minnan.exit, label %cond.else.i
+
+cond.else.i:                                      ; preds = %entry
+  %0 = tail call float @llvm.minnan.f32(float %a, float %b) nounwind readnone
+  br label %test_minnan.exit
+
+test_minnan.exit:                                   ; preds = %cond.else.i, %entry
+  %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+  store float %cond.i, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; ALL-LABEL: @maxnan_test(
+; ALL: select
+define void @maxnan_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+entry:
+  %cmp.i = fcmp olt float %a, 0.000000e+00
+  br i1 %cmp.i, label %test_maxnan.exit, label %cond.else.i
+
+cond.else.i:                                      ; preds = %entry
+  %0 = tail call float @llvm.maxnan.f32(float %a, float %b) nounwind readnone
+  br label %test_maxnan.exit
+
+test_maxnan.exit:                                   ; preds = %cond.else.i, %entry
+  %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+  store float %cond.i, float addrspace(1)* %out, align 4
+  ret void
+}

unittests/ADT/APFloatTest.cpp

TEST(APFloatTest, MaxNum) {
   APFloat nan = APFloat::getNaN(APFloat::IEEEdouble());
 
   EXPECT_EQ(2.0, maxnum(f1, f2).convertToDouble());
   EXPECT_EQ(2.0, maxnum(f2, f1).convertToDouble());
   EXPECT_EQ(1.0, maxnum(f1, nan).convertToDouble());
   EXPECT_EQ(1.0, maxnum(nan, f1).convertToDouble());
 }
 
+TEST(APFloatTest, MinNan) {
+  APFloat f1(1.0);
+  APFloat f2(2.0);
+  APFloat nan = APFloat::getNaN(APFloat::IEEEdouble());
+
+  EXPECT_EQ(1.0, minnan(f1, f2).convertToDouble());
+  EXPECT_EQ(1.0, minnan(f2, f1).convertToDouble());
+  EXPECT_TRUE(std::isnan(minnan(f1, nan).convertToDouble()));
+  EXPECT_TRUE(std::isnan(minnan(nan, f1).convertToDouble()));
+}
+
+TEST(APFloatTest, MaxNan) {
+  APFloat f1(1.0);
+  APFloat f2(2.0);
+  APFloat nan = APFloat::getNaN(APFloat::IEEEdouble());
+
+  EXPECT_EQ(2.0, maxnan(f1, f2).convertToDouble());
+  EXPECT_EQ(2.0, maxnan(f2, f1).convertToDouble());
+  EXPECT_TRUE(std::isnan(maxnan(f1, nan).convertToDouble()));
+  EXPECT_TRUE(std::isnan(maxnan(nan, f1).convertToDouble()));
+}
+
 TEST(APFloatTest, Denormal) {
   APFloat::roundingMode rdmd = APFloat::rmNearestTiesToEven;
 
   // Test single precision
   {
     const char *MinNormalStr = "1.17549435082228750797e-38";
     EXPECT_FALSE(APFloat(APFloat::IEEEsingle(), MinNormalStr).isDenormal());
     EXPECT_FALSE(APFloat(APFloat::IEEEsingle(), 0.0).isDenormal());

unittests/IR/IRBuilderTest.cpp

TEST_F(IRBuilderTest, Intrinsics) {
   Call = Builder.CreateMinNum(V, V);
   II = cast<IntrinsicInst>(Call);
   EXPECT_EQ(II->getIntrinsicID(), Intrinsic::minnum);
 
   Call = Builder.CreateMaxNum(V, V);
   II = cast<IntrinsicInst>(Call);
   EXPECT_EQ(II->getIntrinsicID(), Intrinsic::maxnum);
 
+  Call = Builder.CreateMinNan(V, V);
+  II = cast<IntrinsicInst>(Call);
+  EXPECT_EQ(II->getIntrinsicID(), Intrinsic::minnan);
+
+  Call = Builder.CreateMaxNan(V, V);
+  II = cast<IntrinsicInst>(Call);
+  EXPECT_EQ(II->getIntrinsicID(), Intrinsic::maxnan);
+
   Call = Builder.CreateIntrinsic(Intrinsic::readcyclecounter);
   II = cast<IntrinsicInst>(Call);
   EXPECT_EQ(II->getIntrinsicID(), Intrinsic::readcyclecounter);
 }
 
 TEST_F(IRBuilderTest, Lifetime) {
   IRBuilder<> Builder(BB);
   AllocaInst *Var1 = Builder.CreateAlloca(Builder.getInt8Ty());