[WebAssembly] SIMD conversions

[tlively]

Summary

Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to
int conversions produce poison values if their arguments are out of
the convertible range, so a future CL will have to add an LLVM
intrinsic to make the saturating behavior of this conversion usable.

[tlively]

The actual naming of these instructions is blocked on the bikeshedding discussion at https://github.com/WebAssembly/nontrapping-float-to-int-conversions/issues/4. For the time being, the instructions here have been renamed to avoid colons and slashes have been replaced with question marks to satisfy the lexer (lib/MC/MCParser/AsmLexer.cpp).

[tlively]

Tests need fixing.

[tlively]

• Fix tests

[aheejin]

1. Is it correct to translate those llvm instructions to saturating versions of wasm instructions? For example, for scalars, we had a patch that implemented the saturating behavior. Don't we need a similar thing for vectors too?
2. Is this behavior also dependent on [[ https://github.com/llvm-mirror/llvm/blob/59895038204bec7cb4f924acf25b91f3056ea492/lib/Target/WebAssembly/WebAssembly.td#L30-L33 | nontrapping-fptoint ]] feature, as the scalar instructions?

[aheejin]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

388

It looks like after D52442 we can use the old names?

[sunfish]

In D52372#1244158, @aheejin wrote:

1. Is it correct to translate those llvm instructions to saturating versions of wasm instructions? For example, for scalars, we had a patch that implemented the saturating behavior. Don't we need a similar thing for vectors too?

No: the extra lowering code in that patch is needed when using the trapping forms (which is what MVP wasm has). When -mnontrapping-fptoint is specified, the non-trapping forms are used, which don't need extra lowering code. For SIMD the plan is that we'll only have the saturating forms, so it doesn't need the extra lowering code.

2. Is this behavior also dependent on [[ https://github.com/llvm-mirror/llvm/blob/59895038204bec7cb4f924acf25b91f3056ea492/lib/Target/WebAssembly/WebAssembly.td#L30-L33 | nontrapping-fptoint ]] feature, as the scalar instructions?

No, I don't think we need to do that. We need a flag for scalar because wasm MVP only has the trapping forms, but for SIMD, the plan is to only have the saturating ones, so I think it's safe to assume that if the subtarget has SIMD, it includes those.

[aheejin]

@sunfish Oh I see. Thank you!

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

388

Yep! Done in D52512 so we can get things in more incrementally.

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
   defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
                               !add(baseInst, 1)>;
 }
 multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
   defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
                            [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
                            vec#".abs\t$dst, $vec", vec#".abs", simdop>;
 }
+multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
+                       string name, bits<32> simdop> {
+  defm op#_#vec_t#_#arg_t :
+    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
+           name#"\t$dst, $vec", name, simdop>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,

 defm GT : SIMDConditionFP<"gt", SETOGT, 113>;
 defm GE_S : SIMDConditionInt<"ge_s", SETGE, 115, 2>;
 defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 116, 2>;
 defm GE : SIMDConditionFP<"ge", SETOGE, 123>;
 
 defm "" : SIMDAbs<v4f32, "f32x4", 127>;
 defm "" : SIMDAbs<v2f64, "f64x2", 128>;
 
+defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_s?i32x4", 143>;
+defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_u?i32x4", 144>;
+defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_s?i64x2", 145>;
+defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_u?i64x2", 146>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_saturating_s?f32x4", 143>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_saturating_u?f32x4", 144>;
+defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_saturating_s?f64x2", 145>;
+defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_saturating_u?f64x2", 146>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 
 def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;

test/CodeGen/WebAssembly/simd-conversions.ll

+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
+; Test that vector float-to-int and int-to-float instructions lower correctly
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: convert_s_v4f32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.convert_s?i32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x float> @convert_s_v4f32(<4 x i32> %x) {
+  %a = sitofp <4 x i32> %x to <4 x float>
+  ret <4 x float> %a
+}
+
+; CHECK-LABEL: convert_u_v4f32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.convert_u?i32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x float> @convert_u_v4f32(<4 x i32> %x) {
+  %a = uitofp <4 x i32> %x to <4 x float>
+  ret <4 x float> %a
+}
+
+; CHECK-LABEL: convert_s_v2f64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: f64x2.convert_s?i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.convert_s?i64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
+  %a = sitofp <2 x i64> %x to <2 x double>
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: convert_u_v2f64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: f64x2.convert_u?i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.convert_u?i64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
+  %a = uitofp <2 x i64> %x to <2 x double>
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: trunc_saturating_s_v4i32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.trunc_saturating_s?f32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x i32> @trunc_saturating_s_v4i32(<4 x float> %x) {
+  %a = fptosi <4 x float> %x to <4 x i32>
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: trunc_saturating_u_v4i32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.trunc_saturating_u?f32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x i32> @trunc_saturating_u_v4i32(<4 x float> %x) {
+  %a = fptoui <4 x float> %x to <4 x i32>
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: trunc_saturating_s_v2i64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: i64x2.trunc_saturating_s?f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i64x2.trunc_saturating_s?f64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x i64> @trunc_saturating_s_v2i64(<2 x double> %x) {
+  %a = fptosi <2 x double> %x to <2 x i64>
+  ret <2 x i64> %a
+}
+
+; CHECK-LABEL: trunc_saturating_u_v2i64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: i64x2.trunc_saturating_u?f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i64x2.trunc_saturating_u?f64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x i64> @trunc_saturating_u_v2i64(<2 x double> %x) {
+  %a = fptoui <2 x double> %x to <2 x i64>
+  ret <2 x i64> %a
+}

test/MC/WebAssembly/simd-encodings.s

# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
     f64x2.div
 
     # CHECK: f32x4.mul # encoding: [0xfd,0x8b]
     f32x4.mul
 
     # CHECK: f64x2.mul # encoding: [0xfd,0x8c]
     f64x2.mul
 
+    # CHECK: f32x4.convert_s?i32x4 # encoding: [0xfd,0x8f]
+    f32x4.convert_s?i32x4
+
+    # CHECK: f32x4.convert_u?i32x4 # encoding: [0xfd,0x90]
+    f32x4.convert_u?i32x4
+
+    # CHECK: f64x2.convert_s?i64x2 # encoding: [0xfd,0x91]
+    f64x2.convert_s?i64x2
+
+    # CHECK: f64x2.convert_u?i64x2 # encoding: [0xfd,0x92]
+    f64x2.convert_u?i64x2
+
+    # CHECK? i32x4.trunc_saturating_s?f32x4 # encoding: [0xfd,0x93]
+    i32x4.trunc_saturating_s?f32x4
+
+    # CHECK? i32x4.trunc_saturating_u?f32x4 # encoding: [0xfd,0x94]
+    i32x4.trunc_saturating_u?f32x4
+
+    # CHECK? i64x2.trunc_saturating_s?f64x2 # encoding: [0xfd,0x95]
+    i64x2.trunc_saturating_s?f64x2
+
+    # CHECK? i64x2.trunc_saturating_u?f64x2 # encoding: [0xfd,0x96]
+    i64x2.trunc_saturating_u?f64x2
+
     end_function