[AMDGPU] Load divergence predicate refactoring

[alex-t]

Summary

This change is refactoring of the SMRD load divergence predicate function.
No additional tests needed. Existing smrd and uniformity tests behave as before.

CodeGen/AMDGPU lit tests passed.

[rampitec]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

2121

The name is misleading. A uniform load is just !N->isDivergent(). What you have here is a check if load is actually scalarizable.

2125

The formatting is weird.

[alex-t]

Formatting fixed, function renamed.

[rampitec]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

2125

It is still weird and misleading.

[alex-t]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

2125

Current formatting is done by clang-format -style=llvm.
Could you suggest the way to change it? What style would you prefer?

[rampitec]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

2125

Never mind, that was bogus browser fonts.

[rampitec]

LGTM

[lebedev.ri]

*Please* don't forget to subscribe the appropriate -commits list, and set the appropriate repository!
if that doesn't happen, the review essentially did not happen.

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

 protected:
   void SelectBuildVector(SDNode *N, unsigned RegClassID);
 
 private:
   std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
   bool isNoNanSrc(SDValue N) const;
   bool isInlineImmediate(const SDNode *N) const;
   bool isVGPRImm(const SDNode *N) const;
+  bool isScalarLoad(const SDNode *N) const;
   bool isUniformBr(const SDNode *N) const;
 
   MachineSDNode *buildSMovImm64(SDLoc &DL, uint64_t Val, EVT VT) const;
 
   SDNode *glueCopyToM0(SDNode *N) const;
 
   const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
   virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
if (RC != &AMDGPU::VS_32RegClass) {
       // other user instructions.
       if (!AllUsesAcceptSReg)
         break;
     }
   }
   return !AllUsesAcceptSReg && (Limit < 10);
 }
 
+bool AMDGPUDAGToDAGISel::isScalarLoad(const SDNode *N) const {
+  auto Ld = cast<LoadSDNode>(N);
+
+  return Ld->getAlignment() >= 4 &&
+    (((Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
+      Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
+      !N->isDivergent()) ||
+      (Subtarget->getScalarizeGlobalBehavior() &&
+        Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+        !Ld->isVolatile() && !N->isDivergent() &&
+        static_cast<const SITargetLowering *>(getTargetLowering())
+        ->isMemOpHasNoClobberedMemOperand(N)));
+}
 
 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
   const AMDGPUTargetLowering& Lowering =
     *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
   bool IsModified = false;
   do {
     IsModified = false;
 

lib/Target/AMDGPU/SMInstructions.td

 defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
 }
 
 //===----------------------------------------------------------------------===//
 // Scalar Memory Patterns
 //===----------------------------------------------------------------------===//
 
 
-def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
-  auto Ld = cast<LoadSDNode>(N);
-  return Ld->getAlignment() >= 4  &&
-    ((((Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) || (Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)) && !N->isDivergent()) ||
-    (Subtarget->getScalarizeGlobalBehavior() && Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
-     !Ld->isVolatile() && !N->isDivergent() &&
-    static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)));
-}]>;
+def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isScalarLoad(N);}]>;
 
 def SMRDImm         : ComplexPattern<i64, 2, "SelectSMRDImm">;
 def SMRDImm32       : ComplexPattern<i64, 2, "SelectSMRDImm32">;
 def SMRDSgpr        : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
 def SMRDBufferImm   : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
 
 multiclass SMRD_Pattern <string Instr, ValueType vt> {