[AArch64] Add support for the ABS dag node and testcases for integer abs.

[ikulagin]

Summary

Indicate that the ABS is legal for the i64 type when the NEON is supported.

These changes are related to D49837.

[RKSimon]

test/CodeGen/AArch64/iabs.ll

1

Commit this file with current codegen and update the patch to show the codegen diff?

[ikulagin]

Commit this file with current codegen and update the patch to show the codegen diff?

I have updated this patch.

[RKSimon]

In D51873#1232374, @ikulagin wrote:

Commit this file with current codegen and update the patch to show the codegen diff?

I have updated this patch.

Just commit the test file with trunk's current codegen and then update this phab with the codegen changes - no need for a second phab.

[ikulagin]

In D51873#1232859, @RKSimon wrote:

In D51873#1232374, @ikulagin wrote:

Commit this file with current codegen and update the patch to show the codegen diff?

I have updated this patch.

Just commit the test file with trunk's current codegen and then update this phab with the codegen changes - no need for a second phab.

I'm sorry, I haven't the commit access.

[RKSimon]

Please rebase after rL342156

[ikulagin]

Please rebase after rL342156

Rebase

[RKSimon]

Cheers - this is up to the arm guys now

lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
 
     addQRTypeForNEON(MVT::v4f32);
     addQRTypeForNEON(MVT::v2f64);
     addQRTypeForNEON(MVT::v16i8);
     addQRTypeForNEON(MVT::v8i16);
     addQRTypeForNEON(MVT::v4i32);
     addQRTypeForNEON(MVT::v2i64);
     addQRTypeForNEON(MVT::v8f16);
+
+    // The AArch64 SIMD extension supports the scalar variant
+    // of the ABS instruction.
+    setOperationAction(ISD::ABS, MVT::i64, Legal);
   }
 
   // Compute derived properties from the register classes
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
   // Provide all sorts of operation actions
   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
   setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);

test/CodeGen/AArch64/iabs.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 define i8 @test_i8(i8 %a) nounwind {
 ; CHECK-LABEL: test_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  sbfx w8, w0, #7, #1
-; CHECK-NEXT:  add w9, w0, w8
-; CHECK-NEXT:  eor w0, w9, w8
+; CHECK-NEXT:  sxtb w8, w0
+; CHECK-NEXT:  cmp w8, #0
+; CHECK-NEXT:  cneg w0, w8, mi
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i8 0, %a
   %b = icmp sgt i8 %a, -1
   %abs = select i1 %b, i8 %a, i8 %tmp1neg
   ret i8 %abs
 }
 
 define i16 @test_i16(i16 %a) nounwind {
 ; CHECK-LABEL: test_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  sbfx w8, w0, #15, #1
-; CHECK-NEXT:  add w9, w0, w8
-; CHECK-NEXT:  eor w0, w9, w8
+; CHECK-NEXT:  sxth w8, w0
+; CHECK-NEXT:  cmp w8, #0
+; CHECK-NEXT:  cneg w0, w8, mi
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
   %abs = select i1 %b, i16 %a, i16 %tmp1neg
   ret i16 %abs
 }
 
 define i32 @test_i32(i32 %a) nounwind {
 ; CHECK-LABEL: test_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:  cmp w0, #0
 ; CHECK-NEXT:  cneg w0, w0, mi
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i32 0, %a
   %b = icmp sgt i32 %a, -1
   %abs = select i1 %b, i32 %a, i32 %tmp1neg
   ret i32 %abs
 }
 
 define i64 @test_i64(i64 %a) nounwind {
 ; CHECK-LABEL: test_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  cmp x0, #0
-; CHECK-NEXT:  cneg x0, x0, mi
+; CHECK-NEXT:  fmov d0, x0
+; CHECK-NEXT:  abs d0, d0
+; CHECK-NEXT:  fmov x0, d0
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1
   %abs = select i1 %b, i64 %a, i64 %tmp1neg
   ret i64 %abs
 }