This will be useful to generate many configurations and test instruction regimes (NaN, Inf, subnormal, normal).
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I suppose that will help de-flake the latency measurements? (i *think* i have only seen the fp ops being flaky)
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Yes indeed. For instance SSE/AVX operations may have different regimes depending on their inputs.
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Are these the only values you're going to test? For instance many fdiv units have fast paths for some (+/-)pow2 divisors.