[X86] Make Feature64Bit useful

[craig.topper]

Summary

We now only add +64bit to the CPU string for "generic" CPU. All other CPU names are assumed to have the feature flag already set if they support 64-bit. I've remove the implies from CMPXCHG8 so that Feature64Bit only comes in via CPUs or user passing -mattr=+64bit.

I've changed the assert to a report_fatal_error so it's not lost in Release builds.

The test updates are to fix things that tripped error now.

[efriedma]

We could use the feature bit to try to catch invalid CPU specifications (like trying to use -mcpu=pentium on a 64-bit target).

[efriedma]

Testcase?

[craig.topper]

Updated cpus.ll test to also check for this new error. Had to add a function body to get it to create the X86Subtarget correctly to make the check and had to fix some of the old RUN lines to not pass a 64-bit triple with a 32-bit cpu when they expect no error.

[craig.topper]

Forgot to drop an InstCombine patch from my tree before uploading that last patch.

[efriedma]

LGTM

[anna]

With this change, we now break the code gen in KVMs that do not have the "+64bit" feature tagged (although it is capable of generating 64 bit code). Is there a way to identify the feature for KVMs?

This is the cpuinfo for the KVM where code gen was failing with the Fatal Error: 64-bit code requested on a subtarget that doesn't support it!

cat /proc/cpuinfo:
> processor       : 0
> vendor_id       : AuthenticAMD
> cpu family      : 6
> model           : 13
> model name      : QEMU Virtual CPU version 1.5.3
> stepping        : 3
> microcode       : 0x1000065
> cpu MHz         : 2599.998
> cache size      : 512 KB
> physical id     : 0
> siblings        : 1
> core id         : 0
> cpu cores       : 1
> apicid          : 0
> initial apicid  : 0
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 4
> wp              : yes
> flags           : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx lm nopl pni cx16 hypervisor lahf_lm abm sse4a 3dnowprefetch vmmcall
> bugs            : fxsave_leak sysret_ss_attrs
> bogomips        : 5199.99
> TLB size        : 1024 4K pages
> cache_alignment : 64
> address sizes   : 48 bits physical, 48 bits virtual
> power management:

[craig.topper]

@anna, the "lm" in the flags from the cpuinfo should be the 64bit flag. Is this failing with clang, or llc, or some other program that uses llvm libraries?

[anna]

In D51231#1243547, @craig.topper wrote:

@anna, the "lm" in the flags from the cpuinfo should be the 64bit flag. Is this failing with clang, or llc, or some other program that uses llvm libraries?

Interesting. It's failing with our Azul JIT (Falcon) which uses the llvm libraries.
We populate the features using llvm's sys::getHostCPUFeatures and set the mcpu and mattr in the EngineBuilder.
Note that if I manually add "+64bit" in the feature population (after all features retrieved by getHostCPUFeatures have been added into the mattr), there is no code gen failure on the KVM.

[craig.topper]

We may not be inferring +64bit in getHostCPUFeatures at first glance. I'll check more thoroughly.

[craig.topper]

@anna, hopefully I fixed your issue in r342914

[anna]

In D51231#1243765, @craig.topper wrote:

@anna, hopefully I fixed your issue in r342914

great, thanks @craig.topper! It fixed my issue.

lib/Target/X86/X86.td

 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
                                       "Enable MMX instructions">;
 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
                                       "Enable 3DNow! instructions",
                                       [FeatureMMX]>;
 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
                                       "Enable 3DNow! Athlon instructions",
                                       [Feature3DNow]>;
-// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
-// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
-// without disabling 64-bit mode.
-def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
-                                      "Support 64-bit instructions">;
 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
-                                      "64-bit with cmpxchg16b",
-                                      [Feature64Bit]>;
+                                      "64-bit with cmpxchg16b">;
 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
                                        "SHLD instruction is slow">;
 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
                                         "PMULLD instruction is slow">;
 // FIXME: This should not apply to CPUs that do not have SSE.
 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
                                 "IsUAMem16Slow", "true",
                                 "Slow unaligned 16-byte memory access">;

 
 foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, FeatureSSE1,
                  Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
 }
 
 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
-                 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD,
+                 FeatureFXSR, FeatureNOPL, FeatureSlowSHLD,
                  FeatureCMOV]>;
 }
 
 foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
                  FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD,
                  FeatureCMOV]>;
 }

 // forming a common base for them.
 def : ProcessorModel<"x86-64", SandyBridgeModel, [
   FeatureX87,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE2,
   FeatureFXSR,
   FeatureNOPL,
-  Feature64Bit,
   FeatureSlow3OpsLEA,
   FeatureSlowIncDec,
   FeatureMacroFusion
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//

lib/Target/X86/X86Subtarget.h

protected:
   /// True if this processor has NOPL instruction
   /// (generally pentium pro+).
   bool HasNOPL = false;
 
   /// True if this processor has conditional move instructions
   /// (generally pentium pro+).
   bool HasCMov = false;
 
-  /// True if the processor supports X86-64 instructions.
-  bool HasX86_64 = false;
-
   /// True if the processor supports POPCNT.
   bool HasPOPCNT = false;
 
   /// True if the processor supports SSE4A instructions.
   bool HasSSE4A = false;
 
   /// Target has AES instructions
   bool HasAES = false;

lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   if (CPUName.empty())
     CPUName = "generic";
 
   // Make sure 64-bit features are available in 64-bit mode. (But make sure
   // SSE2 can be turned off explicitly.)
   std::string FullFS = FS;
   if (In64BitMode) {
     if (!FullFS.empty())
-      FullFS = "+64bit,+sse2," + FullFS;
+      FullFS = "+sse2," + FullFS;
     else
-      FullFS = "+64bit,+sse2";
+      FullFS = "+sse2";
   }
 
   // LAHF/SAHF are always supported in non-64-bit mode.
   if (!In64BitMode) {
     if (!FullFS.empty())
       FullFS = "+sahf," + FullFS;
     else
       FullFS = "+sahf";
else if (In32BitMode)
     ToggleFeature(X86::Mode32Bit);
   else if (In16BitMode)
     ToggleFeature(X86::Mode16Bit);
   else
     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
 
   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
-                    << HasX86_64 << "\n");
-  assert((!In64BitMode || HasX86_64) &&
-         "64-bit code requested on a subtarget that doesn't support it!");
+                    << In64BitMode << "\n");
 
   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
   // 32 and 64 bit) and for all 64-bit targets.
   if (StackAlignOverride)
     stackAlignment = StackAlignOverride;
   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
            isTargetKFreeBSD() || In64BitMode)
     stackAlignment = 16;

test/CodeGen/X86/sse_reload_fold.ll

-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=basic 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 -print-failed-fuse-candidates -regalloc=basic 2>&1 | FileCheck %s
 ; CHECK: fail
 ; CHECK-NOT: fail
 
 declare float @test_f(float %f)
 declare double @test_d(double %f)
 declare <4 x float> @test_vf(<4 x float> %f)
 declare <2 x double> @test_vd(<2 x double> %f)
 declare float @llvm.sqrt.f32(float)

test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll

-; RUN: llc  -mtriple=x86_64-apple-macosx10.9.0  -mcpu=core2 -mattr=+64bit,+sse2 < %s | FileCheck %s
+; RUN: llc  -mtriple=x86_64-apple-macosx10.9.0  -mcpu=core2 -mattr=+sse2 < %s | FileCheck %s
 
 ; DAGCombine may choose to rewrite 2 loads feeding a select as a select of
 ; addresses feeding a load. This test ensures that when it does that it creates
 ; a load with alignment equivalent to the most restrictive source load.
 
 declare void @sink(<2 x double>)
 
 define void @test1(i1 %cmp) align 2 {