[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions

[jkolek]

Summary

Implement microMIPS 16-bit LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions.

[jkolek]

Added instruction LBU16. Fixed offset shifting for the instructions SBU16, SHU16, LHU16.

[sstankovic]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1174

Allowed offsets for lbu16 and sb16 are different. lbu16 requires [-1, 0, ..., 14], sb16 requires [0, 1, ..., 15].

1183

Allowed offsets for lhu16 and sh16 are [0, 2, ..., 30] (4-bit unsigned, shifted left by one).

1192

Allowed offsets for lw16 and sw16 are [0, 4, ..., 60] (4-bit unsigned, shifted left by two).

lib/Target/Mips/MicroMipsInstrInfo.td

285

For sb16, sh16 and sw16, allowed values for a source register ($rt) are $0, $2-$7 and $17, so GPRMM16Opnd (which represents $2-$7, $16 and $17) cannot be used.

test/MC/Mips/micromips-16-bit-instructions.s

83

You should also check that $0 is allowed as a source register for store.

test/MC/Mips/micromips-invalid.s

27

You should also check that error is reported if base reg is not one of $2-$7, $16 and $17.

[jkolek]

• Fixed operand ranges in MipsAsmParser::processInstruction() for the instructions: SB16, LHU16, SH16, LW16, SW16,
• Also, SB16, SH16, SW16 are using GPRMM16OpndZero for register $rt,
• Added check in micromips-16-bit-instructions.s to ensure that $0 is valid operand for $rt register of SW16 (i.e. SH16, SB16),
• Added checks for invalid operands in micromips-invalid for LBU16, SB16, LHU16, SH16, LW16, SW16.

[sstankovic]

test/MC/Mips/micromips-invalid.s

30

You still don't have a test that checks that error is reported if invalid base register is specified. These 3 lines do have invalid base register ($9 and $10), but they have invalid offset too, and the error that is reported is the error for the offset.

[jkolek]

Added test cases to check invalid base registers.

[sstankovic]

LGTM, with 2 changes.

lib/Target/Mips/MicroMipsInstrInfo.td

149

This line doesn't fit in 80 columns.

270

Move this line one space to the right.

[jkolek]

Closed by commit rL222653 (authored by @jkolek).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
         }
       }
     } // for
   }   // if load/store
 
   if (inMicroMipsMode()) {
     MCOperand Opnd;
     int Imm;
+    unsigned UImm;
 
     switch (Inst.getOpcode()) {
       default:
         break;
       case Mips::ADDIUS5_MM:
         Opnd = Inst.getOperand(2);
         if (!Opnd.isImm())
           return Error(IDLoc, "expected immediate operand kind");
switch (Inst.getOpcode()) {
       case Mips::SRL16_MM:
         Opnd = Inst.getOperand(2);
         if (!Opnd.isImm())
           return Error(IDLoc, "expected immediate operand kind");
         Imm = Opnd.getImm();
         if (Imm < 1 || Imm > 7)
           return Error(IDLoc, "immediate operand value out of range");
         break;
+      case Mips::LHU16_MM:
+      case Mips::LW16_MM:
+      case Mips::SB16_MM:
+      case Mips::SH16_MM:
+      case Mips::SW16_MM:
+        Opnd = Inst.getOperand(2);
+        if (!Opnd.isImm())
+          return Error(IDLoc, "expected immediate operand kind");
+        UImm = Opnd.getImm();
+        if (UImm > 60)
+          return Error(IDLoc, "immediate operand value out of range");
+        break;
     }
   }
 
   if (needsExpansion(Inst))
     return expandInstruction(Inst, IDLoc, Instructions);
   else
     Instructions.push_back(Inst);
 
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::LoadImm64Reg:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
   switch (Inst.getOpcode()) {
   default:
     assert(0 && "unimplemented expansion");
     return true;
   case Mips::LoadImm32Reg:
     return expandLoadImm(Inst, IDLoc, Instructions);
   case Mips::LoadImm64Reg:
     if (!isGP64bit()) {
       Error(IDLoc, "instruction requires a CPU feature not currently enabled");
       return true;
     }
     return expandLoadImm(Inst, IDLoc, Instructions);
   case Mips::LoadAddr32Imm:
     return expandLoadAddressImm(Inst, IDLoc, Instructions);
   case Mips::LoadAddr32Reg:
     return expandLoadAddressReg(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <bool PerformShift>
 void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                    SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
   if (PerformShift) {
     tmpInst.setOpcode(Mips::DSLL);

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

public:
 
   unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const;
+  unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
+                                SmallVectorImpl<MCFixup> &Fixups,
+                                const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
   unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
   unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
   assert(MI.getOperand(OpNo).isReg());
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
 
   return (OffBits & 0xFFFF) | RegBits;
 }
 
 unsigned MipsMCCodeEmitter::
+getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
+                     SmallVectorImpl<MCFixup> &Fixups,
+                     const MCSubtargetInfo &STI) const {
+  // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
+  assert(MI.getOperand(OpNo).isReg());
+  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
+                                       Fixups, STI) << 4;
+  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
+                                       Fixups, STI) >> 2;
+
+  return (OffBits & 0xF) | RegBits;
+}
+
+unsigned MipsMCCodeEmitter::
 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                       SmallVectorImpl<MCFixup> &Fixups,
                       const MCSubtargetInfo &STI) const {
   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
   assert(MI.getOperand(OpNo).isReg());
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
 

lib/Target/Mips/MicroMipsInstrFormats.td

class SHIFT_FM_MM<bits<1> funct> {
 
   let Inst{15-10} = 0x09;
   let Inst{9-7}   = rd;
   let Inst{6-4}   = rt;
   let Inst{3-1}   = shamt;
   let Inst{0}     = funct;
 }
 
+class LOAD_STORE_FM_MM16<bits<6> op> {
+  bits<3> rt;
+  bits<7> addr;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = op;
+  let Inst{9-7}   = rt;
+  let Inst{6-4}   = addr{6-4};
+  let Inst{3-0}   = addr{3-0};
+}
+
 class ADDIUS5_FM_MM16 {
   bits<5> rd;
   bits<4> imm;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x13;
   let Inst{9-5}   = rd;

lib/Target/Mips/MicroMipsInstrInfo.td

+def addrimm4 : ComplexPattern<iPTR, 2, "selectAddrRegImm6", [frameindex]>;
+
 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
 
 def simm12 : Operand<i32> {
   let DecoderMethod = "DecodeSimm12";
 }
 
 def imm5shr2 : Operand<OtherVT> {
   let EncoderMethod = "getImm5Shr2Value";
 }
 
 def addius5_imm : Operand<i32> {
   let EncoderMethod = "getAddius5Value";
 }
 
 def addiusp_imm : Operand<i32> {
   let EncoderMethod = "getAddiuspValue";
 }
 
 def shift_imm3 : Operand<i32> {
   let EncoderMethod = "getEncodedShiftImm";
 }
 
 def shift_immZExt3 : ImmLeaf<i32, [{return Imm >= 0 && Imm <= 8;}]>;
 
+def mem_mm_4 : Operand<i32> {
+  let PrintMethod = "printMemOperand";
+  let EncoderMethod = "getMemEncodingMMImm4";
+  let ParserMatchClass = MipsMemAsmOperand;
+  let OperandType = "OPERAND_MEMORY";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
                   !strconcat(opstr, "\t$rd, $rt, $shamt"),
                   [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], Itin, FrmR>;
 
 class AddImmUS5<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, addius5_imm:$imm),
                   !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
   let Constraints = "$rd = $dst";
   let isCommutable = 1;
 }
 
+class LoadMM16<string opstr, DAGOperand RO,
+               SDPatternOperator OpNode = null_frag,
+               InstrItinClass Itin = NoItinerary,
+               ComplexPattern Addr = addrimm4> :
+  MicroMipsInst16<(outs RO:$rt), (ins mem_mm_4:$addr),
+                  !strconcat(opstr, "\t$rt, $addr"),
+                  [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI> {
+  let canFoldAsLoad = 1;
+  let mayLoad = 1;
+}
+
+class StoreMM16<string opstr, DAGOperand RO,
+                SDPatternOperator OpNode = null_frag,
+                InstrItinClass Itin = NoItinerary,
+                ComplexPattern Addr = addrimm4> :
+  MicroMipsInst16<(outs), (ins RO:$rt, mem_mm_4:$addr),
+                  !strconcat(opstr, "\t$rt, $addr"),
+                  [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI> {
+  let mayStore = 1;
+}
+
 class AddImmUSP<string opstr> :
   MicroMipsInst16<(outs), (ins addiusp_imm:$imm),
                   !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
 
 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
   [], II_MFHI_MFLO, FrmR> {
   let Uses = [UseReg];
def OR16_MM  : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
                LOGIC_FM_MM16<0x3>;
 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
                LOGIC_FM_MM16<0x1>;
 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
 def SLL16_MM : ShiftIMM16<"sll16", shift_imm3, GPRMM16Opnd, shl,
                           shift_immZExt3, II_SLL>, SHIFT_FM_MM<0>;
 def SRL16_MM : ShiftIMM16<"srl16", shift_imm3, GPRMM16Opnd, srl,
                           shift_immZExt3, II_SRL>, SHIFT_FM_MM<1>;
+def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU>,
+               LOAD_STORE_FM_MM16<0x0a>;
+def LW16_MM  : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW>,
+               LOAD_STORE_FM_MM16<0x1a>;
+def SB16_MM  : StoreMM16<"sb16", GPRMM16Opnd, truncstorei8, II_SB>,
+               LOAD_STORE_FM_MM16<0x22>;
+def SH16_MM  : StoreMM16<"sh16", GPRMM16Opnd, truncstorei16, II_SH>,
+               LOAD_STORE_FM_MM16<0x2a>;
+def SW16_MM  : StoreMM16<"sw16", GPRMM16Opnd, store, II_SW>,
+               LOAD_STORE_FM_MM16<0x3a>;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs", GPR32Opnd>, JALR_FM_MM16<0x09>;
 def JRC16_MM : JumpLinkRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
 
 class WaitMM<string opstr> :
   InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
          NoItinerary, FrmOther, opstr>;

lib/Target/Mips/MipsCodeEmitter.cpp

private:
   unsigned getBranchTarget21OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
   unsigned getBranchTarget26OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
   unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const;
 
   unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
+  unsigned getMemEncodingMMImm4(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSimm19Lsl2Encoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSimm18Lsl3Encoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getEncodedShiftImm(const MachineInstr &MI, unsigned OpNo) const;

 unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,
                                          unsigned OpNo) const {
   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
   assert(MI.getOperand(OpNo).isReg());
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
   return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
 }
 
+unsigned MipsCodeEmitter::getMemEncodingMMImm4(const MachineInstr &MI,
+                                               unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getMemEncodingMMImm12(const MachineInstr &MI,
                                                 unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
   return 0;
 }
 
 unsigned MipsCodeEmitter::getMSAMemEncoding(const MachineInstr &MI,
                                             unsigned OpNo) const {

lib/Target/Mips/MipsISelDAGToDAG.h

private:
   /// Fall back on this function if all else fails.
   virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
                                  SDValue &Offset) const;
 
   /// Match integer address pattern.
   virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
                              SDValue &Offset) const;
 
+  virtual bool selectAddrRegImm6(SDValue Addr, SDValue &Base,
+                                 SDValue &Offset) const;
+
   virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
                                SDValue &Offset) const;
 
   /// Match addr+simm10 and addr
   virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
                                 SDValue &Offset) const;
 
   virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,

lib/Target/Mips/MipsISelDAGToDAG.cpp

 }
 
 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
                                      SDValue &Offset) const {
   llvm_unreachable("Unimplemented function.");
   return false;
 }
 
+bool MipsDAGToDAGISel::selectAddrRegImm6(SDValue Addr, SDValue &Base,
+                                         SDValue &Offset) const {
+  llvm_unreachable("Unimplemented function.");
+  return false;
+}
+
 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
                                        SDValue &Offset) const {
   llvm_unreachable("Unimplemented function.");
   return false;
 }
 
 bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
                                         SDValue &Offset) const {

lib/Target/Mips/MipsSEISelDAGToDAG.h

bool selectAddrRegReg(SDValue Addr, SDValue &Base,
                         SDValue &Offset) const override;
 
   bool selectAddrDefault(SDValue Addr, SDValue &Base,
                          SDValue &Offset) const override;
 
   bool selectIntAddr(SDValue Addr, SDValue &Base,
                      SDValue &Offset) const override;
 
+  bool selectAddrRegImm6(SDValue Addr, SDValue &Base, SDValue &Offset) const;
+
   bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
                           SDValue &Offset) const;
 
   bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
                           SDValue &Offset) const;
 
   bool selectIntAddrMM(SDValue Addr, SDValue &Base,
                        SDValue &Offset) const override;

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

 }
 
 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
                                        SDValue &Offset) const {
   return selectAddrRegImm(Addr, Base, Offset) ||
     selectAddrDefault(Addr, Base, Offset);
 }
 
+bool MipsSEDAGToDAGISel::selectAddrRegImm6(SDValue Addr, SDValue &Base,
+                                           SDValue &Offset) const {
+  if (selectAddrFrameIndex(Addr, Base, Offset))
+    return true;
+
+  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 6))
+    return true;
+
+  return false;
+}
+
 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
                                             SDValue &Offset) const {
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
     return true;
 

test/MC/Mips/micromips-16-bit-instructions.s

 # CHECK-EL: addu16  $6, $17, $4     # encoding: [0x42,0x07]
 # CHECK-EL: subu16  $5, $16, $3     # encoding: [0xb1,0x06]
 # CHECK-EL: and16   $16, $2         # encoding: [0x82,0x44]
 # CHECK-EL: not16   $17, $3         # encoding: [0x0b,0x44]
 # CHECK-EL: or16    $16, $4         # encoding: [0xc4,0x44]
 # CHECK-EL: xor16   $17, $5         # encoding: [0x4d,0x44]
 # CHECK-EL: sll16   $3, $16, 5      # encoding: [0x8a,0x25]
 # CHECK-EL: srl16   $4, $17, 6      # encoding: [0x1d,0x26]
+# CHECK-EL: lhu16   $3, 4($16)      # encoding: [0x81,0x29]
+# CHECK-EL: lw16    $4, 8($17)      # encoding: [0x12,0x6a]
+# CHECK-EL: sb16    $3, 4($16)      # encoding: [0x81,0x89]
+# CHECK-EL: sh16    $4, 8($17)      # encoding: [0x12,0xaa]
+# CHECK-EL: sw16    $4, 4($17)      # encoding: [0x11,0xea]
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
 # CHECK-EL: addiusp -255            # encoding: [0x03,0x4e]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-EL: jr16    $9              # encoding: [0x89,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]

 # CHECK-EB: addu16  $6, $17, $4     # encoding: [0x07,0x42]
 # CHECK-EB: subu16  $5, $16, $3     # encoding: [0x06,0xb1]
 # CHECK-EB: and16   $16, $2         # encoding: [0x44,0x82]
 # CHECK-EB: not16   $17, $3         # encoding: [0x44,0x0b]
 # CHECK-EB: or16    $16, $4         # encoding: [0x44,0xc4]
 # CHECK-EB: xor16   $17, $5         # encoding: [0x44,0x4d]
 # CHECK-EB: sll16   $3, $16, 5      # encoding: [0x25,0x8a]
 # CHECK-EB: srl16   $4, $17, 6      # encoding: [0x26,0x1d]
+# CHECK-EB: lhu16   $3, 4($16)      # encoding: [0x29,0x81]
+# CHECK-EB: lw16    $4, 8($17)      # encoding: [0x6a,0x12]
+# CHECK-EB: sb16    $3, 4($16)      # encoding: [0x89,0x81]
+# CHECK-EB: sh16    $4, 8($17)      # encoding: [0xaa,0x12]
+# CHECK-EB: sw16    $4, 4($17)      # encoding: [0xea,0x11]
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
 # CHECK-EB: addiusp -255            # encoding: [0x4e,0x03]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-EB: jr16    $9              # encoding: [0x45,0x89]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalr    $9              # encoding: [0x45,0xc9]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalrs   $9              # encoding: [0x45,0x29]
 # CHECK-EB: move    $zero, $zero    # encoding: [0x0c,0x00]
 # CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 
     addu16  $6, $17, $4
     subu16  $5, $16, $3
     and16   $16, $2
     not16   $17, $3
     or16    $16, $4
     xor16   $17, $5
     sll16   $3, $16, 5
     srl16   $4, $17, 6
+    lhu16   $3, 4($16)
+    lw16    $4, 8($17)
+    sb16    $3, 4($16)
+    sh16    $4, 8($17)
+    sw16    $4, 4($17)
     addius5 $7, -2
     addiusp -255
     mfhi    $9
     mflo    $9
     move    $25, $1
     jrc     $9
     jr16    $9
     jalr    $9
     jalrs   $9
     jraddiusp 20

test/MC/Mips/micromips-invalid.s

 # RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1
 # RUN: FileCheck %s < %t1
 
   addu16  $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   subu16  $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   and16   $16, $8   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   not16   $18, $9   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   or16    $16, $10  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   xor16   $15, $5   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sll16   $1, $16, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   srl16   $4, $9, 6  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sll16   $3, $16, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   srl16   $4, $5, 15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lw16  $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sb16  $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sh16  $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sw16  $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  lw16  $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  sb16  $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  sh16  $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  sw16  $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range