Implement microMIPS 16-bit LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions.
|1174 ↗||(On Diff #14272)|
Allowed offsets for lbu16 and sb16 are different. lbu16 requires [-1, 0, ..., 14], sb16 requires [0, 1, ..., 15].
|1183 ↗||(On Diff #14272)|
Allowed offsets for lhu16 and sh16 are [0, 2, ..., 30] (4-bit unsigned, shifted left by one).
|1192 ↗||(On Diff #14272)|
Allowed offsets for lw16 and sw16 are [0, 4, ..., 60] (4-bit unsigned, shifted left by two).
|285 ↗||(On Diff #14272)|
For sb16, sh16 and sw16, allowed values for a source register ($rt) are $0, $2-$7 and $17, so GPRMM16Opnd (which represents $2-$7, $16 and $17) cannot be used.
|83 ↗||(On Diff #14272)|
You should also check that $0 is allowed as a source register for store.
|27 ↗||(On Diff #14272)|
You should also check that error is reported if base reg is not one of $2-$7, $16 and $17.
- Fixed operand ranges in MipsAsmParser::processInstruction() for the instructions: SB16, LHU16, SH16, LW16, SW16,
- Also, SB16, SH16, SW16 are using GPRMM16OpndZero for register $rt,
- Added check in micromips-16-bit-instructions.s to ensure that $0 is valid operand for $rt register of SW16 (i.e. SH16, SB16),
- Added checks for invalid operands in micromips-invalid for LBU16, SB16, LHU16, SH16, LW16, SW16.
|30 ↗||(On Diff #14882)|
You still don't have a test that checks that error is reported if invalid base register is specified. These 3 lines do have invalid base register ($9 and $10), but they have invalid offset too, and the error that is reported is the error for the offset.