@@ -46,6 +46,32 @@ def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
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def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
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+ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
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+ let Name = "MicroMipsMem";
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+ let RenderMethod = "addMicroMipsMemOperands";
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+ let ParserMethod = "parseMemOperand";
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+ let PredicateMethod = "isMemWithGRPMM16Base";
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+ }
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+
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+ class mem_mm_4_generic : Operand<i32> {
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+ let PrintMethod = "printMemOperand";
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+ let MIOperandInfo = (ops ptr_rc, simm4);
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+ let OperandType = "OPERAND_MEMORY";
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+ let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
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+ }
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+
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+ def mem_mm_4 : mem_mm_4_generic {
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+ let EncoderMethod = "getMemEncodingMMImm4";
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+ }
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+
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+ def mem_mm_4_lsl1 : mem_mm_4_generic {
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+ let EncoderMethod = "getMemEncodingMMImm4Lsl1";
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+ }
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+
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+ def mem_mm_4_lsl2 : mem_mm_4_generic {
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+ let EncoderMethod = "getMemEncodingMMImm4Lsl2";
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+ }
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+
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def mem_mm_12 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops GPR32, simm12);
@@ -156,6 +182,22 @@ class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
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!strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
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+ class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
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+ InstrItinClass Itin, Operand MemOpnd> :
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+ MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
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+ !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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+ let canFoldAsLoad = 1;
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+ let mayLoad = 1;
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+ }
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+
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+ class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
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+ SDPatternOperator OpNode, InstrItinClass Itin,
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+ Operand MemOpnd> :
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+ MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
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+ !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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+ let mayStore = 1;
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+ }
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+
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class AddImmUR2<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
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!strconcat(opstr, "\t$rd, $rs, $imm"),
@@ -316,6 +358,19 @@ def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
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SHIFT_FM_MM16<0>;
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def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
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SHIFT_FM_MM16<1>;
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+ def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
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+ mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
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+ def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
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+ mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
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+ def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
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+ LOAD_STORE_FM_MM16<0x1a>;
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+ def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
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+ II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
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+ def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
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+ II_SH, mem_mm_4_lsl1>,
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+ LOAD_STORE_FM_MM16<0x2a>;
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+ def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
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+ mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
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def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
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def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
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def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
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