[RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.

[apazos]

Summary

Missing check for isImm() in some Immediate classes.

This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer for the RISC-V assembly language.

[hiraditya]

LGTM.

[apazos]

Updated one more Immediate class.
We should probably update them all, the fuzzer keeps breaking. Let me know.

[apazos]

One more Immediate class check failure.

[apazos]

Added the last immediate fix, it looks like the fuzzer found them all.

[hiraditya]

In D50797#1201220, @apazos wrote:

Updated one more Immediate class.
We should probably update them all, the fuzzer keeps breaking. Let me know.

I think it's okay to merge this one, and if we find more then we can put that in subsequent patches.

[asb]

Looks good to me, thanks. Great to see the fuzzer uncovering bugs like this.

llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool isUImm5NonZero() const {
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isSImm6() const {
+    if (!isImm())
+      return false;
     RISCVMCExpr::VariantKind VK;
     int64_t Imm;
     bool IsValid;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     if (!IsConstantImm)
       IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
     else
       IsValid = isInt<6>(Imm);
     return IsValid &&
            (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO);
   }
 
   bool isSImm6NonZero() const {
+    if (!isImm())
+      return false;
     RISCVMCExpr::VariantKind VK;
     int64_t Imm;
     bool IsValid;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     if (!IsConstantImm)
       IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
     else
       IsValid = ((Imm != 0) && isInt<6>(Imm));
     return IsValid &&
            (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO);
   }
 
   bool isCLUIImm() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && (Imm != 0) &&
            (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) &&
             VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm7Lsb00() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isShiftedUInt<5, 2>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm8Lsb00() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isShiftedUInt<6, 2>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm8Lsb000() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isShiftedUInt<5, 3>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isSImm9Lsb0() const { return isBareSimmNLsb0<9>(); }
 
   bool isUImm9Lsb000() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isShiftedUInt<6, 3>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm10Lsb00NonZero() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isShiftedUInt<8, 2>(Imm) && (Imm != 0) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isSImm12() const {
if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }
 
   bool isSImm10Lsb0000NonZero() const {
+    if (!isImm())
+      return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm20() const {

llvm/trunk/test/MC/RISCV/rv32c-fuzzed-invalid.s

+# REQUIRES: asserts
+# RUN: not llvm-mc -triple riscv32 -mattr=+c,+f,+d < %s 2>&1 | FileCheck %s
+#
+# Fuzzed test cases produced by a LLVM MC Assembler
+# Protocol Buffer Fuzzer for the RISC-V assembly language.
+#
+
+c.addi x13,f30,0    # CHECK: error: immediate must be non-zero in the range [-32, 31]
+c.swsp x0,(f14)     # CHECK: error: immediate must be a multiple of 4 bytes in the range [0, 252]
+c.lui x4,x0         # CHECK: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
+c.li x6,x6,x0,x0    # CHECK: error: immediate must be an integer in the range [-32, 31]
+c.addi16sp 2,(x0)   # CHECK: error: invalid operand for instruction
+c.fsdsp f9,x0,0     # CHECK: error: immediate must be a multiple of 8 bytes in the range [0, 504]
+c.flw f15,x14,x0    # CHECK: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+c.fld f8,f30,x17    # CHECK: error: immediate must be a multiple of 8 bytes in the range [0, 248]
+c.addi4spn x8,x2,x8 # CHECK: error: immediate must be a multiple of 4 bytes in the range [4, 1020]
+