[WebAssembly] SIMD encoding tests

[tlively]

Summary

Modifies existing SIMD tests to also check that SIMD instructions are
lowered to the expected bytes. This CL depends on D50597.

Patch by Thomas Lively

[aheejin]

Didn't know llc has --show-mc-encoding option! 👍 Probably we should start using this elsewhere too.

test/CodeGen/WebAssembly/simd-arith.ll

21

Do we need # at the end here?

[tlively]

test/CodeGen/WebAssembly/simd-arith.ll

21

Not really. One option is to complete the line ; SIMD128: return $pop0 # encoding: [0x0f], Another is to just stop with the $pop0. I had added the # because the test had previously checked for end of line and I didn't want to weaken the test too much.

[aheejin]

test/CodeGen/WebAssembly/simd-arith.ll

1

Change -wasm-register-codegen-test-mode to the old option here too

[tlively]

• Fix llc arguments

test/CodeGen/WebAssembly/simd-arith.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: add_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i8x16.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.add $push0=, $0, $1 # encoding: [0xfd,0x18]{{$}}
+; SIMD128: return $pop0 #
 define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = add <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i8x16.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.sub $push0=, $0, $1 # encoding: [0xfd,0x1c]{{$}}
+; SIMD128: return $pop0 #
 define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = sub <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: mul_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i8x16.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.mul $push0=, $0, $1 # encoding: [0xfd,0x20]{{$}}
+; SIMD128: return $pop0 #
 define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = mul <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_v8i16
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i16x8.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.add $push0=, $0, $1 # encoding: [0xfd,0x19]{{$}}
+; SIMD128: return $pop0 #
 define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = add <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_v8i16
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i16x8.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.sub $push0=, $0, $1 # encoding: [0xfd,0x1d]{{$}}
+; SIMD128: return $pop0 #
 define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = sub <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: mul_v8i16
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i16x8.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.mul $push0=, $0, $1 # encoding: [0xfd,0x21]{{$}}
+; SIMD128: return $pop0 #
 define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = mul <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: add_v4i32
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i32x4.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i32x4.add $push0=, $0, $1 # encoding: [0xfd,0x1a]{{$}}
+; SIMD128: return $pop0 #
 define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = add <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: sub_v4i32
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x1e]{{$}}
+; SIMD128: return $pop0 #
 define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = sub <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: mul_v4i32
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x22]{{$}}
+; SIMD128: return $pop0 #
 define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = mul <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i64x2.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i64x2.add $push0=, $0, $1 # encoding: [0xfd,0x1b]{{$}}
+; SIMD128: return $pop0 #
 define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = add <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: sub_v2i64
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x1f]{{$}}
+; SIMD128: return $pop0 #
 define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = sub <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: mul_v2i64
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x23]{{$}}
+; SIMD128: return $pop0 #
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: add_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f32x4.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f32x4.add $push0=, $0, $1 # encoding: [0xfd,0x7a]{{$}}
+; SIMD128: return $pop0 #
 define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fadd <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: sub_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x7c]{{$}}
+; SIMD128: return $pop0 #
 define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fsub <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: div_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f32x4.div $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f32x4.div $push0=, $0, $1 # encoding: [0xfd,0x7e]{{$}}
+; SIMD128: return $pop0 #
 define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fdiv <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: mul_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x80]{{$}}
+; SIMD128: return $pop0 #
 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: add_v2f64
 ; NO-SIMD128-NOT: f64x2
 ; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f64x2.add $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f64x2.add $push0=, $0, $1 # encoding: [0xfd,0x7b]{{$}}
+; SIMD128: return $pop0 #
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fadd <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: sub_v2f64
 ; NO-SIMD128-NOT: f64x2
 ; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x7d]{{$}}
+; SIMD128: return $pop0 #
 define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fsub <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: div_v2f64
 ; NO-SIMD128-NOT: f64x2
 ; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f64x2.div $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f64x2.div $push0=, $0, $1 # encoding: [0xfd,0x7f]{{$}}
+; SIMD128: return $pop0 #
 define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fdiv <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: mul_v2f64
 ; NO-SIMD128-NOT: f64x2
 ; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
-; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x81]{{$}}
+; SIMD128: return $pop0 #
 define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fmul <2 x double> %x, %y
   ret <2 x double> %a
 }

test/CodeGen/WebAssembly/simd.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 vector manipulation operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
-; CHECK-LABEL: extract_v16i8_s:{{$}}
+; CHECK-LABEL: extract_v16i8_s:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i8x16.extract_lane_s $push0=, $0, 13{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.extract_lane_s $push0=, $0, 13 # encoding: [0xfd,0x09,0x0d]{{$}}
+; SIMD128: return $pop0 #
 define i32 @extract_v16i8_s(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   %a = sext i8 %elem to i32
   ret i32 %a
 }
 
-; CHECK-LABEL: extract_v16i8_u:{{$}}
+; CHECK-LABEL: extract_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
+; SIMD128: return $pop0 #
 define i32 @extract_v16i8_u(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   %a = zext i8 %elem to i32
   ret i32 %a
 }
 
-; CHECK-LABEL: extract_v16i8:{{$}}
+; CHECK-LABEL: extract_v16i8:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
+; SIMD128: return $pop0 #
 define i8 @extract_v16i8(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   ret i8 %elem
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
-; CHECK-LABEL: extract_v8i16_s:{{$}}
+; CHECK-LABEL: extract_v8i16_s:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i16x8.extract_lane_s $push0=, $0, 5{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.extract_lane_s $push0=, $0, 5 # encoding: [0xfd,0x0b,0x05]{{$}}
+; SIMD128: return $pop0 #
 define i32 @extract_v8i16_s(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   %a = sext i16 %elem to i32
   ret i32 %a
 }
 
-; CHECK-LABEL: extract_v8i16_u:{{$}}
+; CHECK-LABEL: extract_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
+; SIMD128: return $pop0 #
 define i32 @extract_v8i16_u(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   %a = zext i16 %elem to i32
   ret i32 %a
 }
 
-; CHECK-LABEL: extract_v8i16:{{$}}
+; CHECK-LABEL: extract_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
+; SIMD128: return $pop0 #
 define i16 @extract_v8i16(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   ret i16 %elem
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
-; CHECK-LABEL: extract_v4i32:{{$}}
+; CHECK-LABEL: extract_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i32{{$}}
-; SIMD128: i32x4.extract_lane $push0=, $0, 3{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0d,0x03]{{$}}
+; SIMD128: return $pop0 #
 define i32 @extract_v4i32(<4 x i32> %v) {
   %elem = extractelement <4 x i32> %v, i32 3
   ret i32 %elem
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
-; CHECK-LABEL: extract_v2i64:{{$}}
+; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i64{{$}}
-; SIMD128: i64x2.extract_lane $push0=, $0, 1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
+; SIMD128: return $pop0 #
 define i64 @extract_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 1
   ret i64 %elem
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
-; CHECK-LABEL: extract_v4f32:{{$}}
+; CHECK-LABEL: extract_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result f32{{$}}
-; SIMD128: f32x4.extract_lane $push0=, $0, 3{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0f,0x03]{{$}}
+; SIMD128: return $pop0 #
 define float @extract_v4f32(<4 x float> %v) {
   %elem = extractelement <4 x float> %v, i32 3
   ret float %elem
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
-; CHECK-LABEL: extract_v2f64:{{$}}
+; CHECK-LABEL: extract_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result f64{{$}}
-; SIMD128: f64x2.extract_lane $push0=, $0, 1{{$}}
-; SIMD128: return $pop0{{$}}
+; SIMD128: f64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x10,0x01]{{$}}
+; SIMD128: return $pop0 #
 define double @extract_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 1
   ret double %elem
 }