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[AMDGPU] New buffer intrinsics
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Authored by tpr on Aug 5 2018, 6:49 AM.

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Summary

This commit adds new intrinsics

llvm.amdgcn.raw.buffer.load
llvm.amdgcn.raw.buffer.load.format
llvm.amdgcn.raw.buffer.load.format.d16
llvm.amdgcn.struct.buffer.load
llvm.amdgcn.struct.buffer.load.format
llvm.amdgcn.struct.buffer.load.format.d16
llvm.amdgcn.raw.buffer.store
llvm.amdgcn.raw.buffer.store.format
llvm.amdgcn.raw.buffer.store.format.d16
llvm.amdgcn.struct.buffer.store
llvm.amdgcn.struct.buffer.store.format
llvm.amdgcn.struct.buffer.store.format.d16
llvm.amdgcn.raw.buffer.atomic.*
llvm.amdgcn.struct.buffer.atomic.*

with the following changes from the llvm.amdgcn.buffer.*
intrinsics:

  • there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set;
  • there is a combined cachepolicy arg (glc+slc)
  • there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field.

The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.

The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.

Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205

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Repository
rL LLVM

Event Timeline

tpr created this revision.Aug 5 2018, 6:49 AM
mareko accepted this revision.Aug 20 2018, 4:23 PM
This revision is now accepted and ready to land.Aug 20 2018, 4:23 PM
Closed by commit rL340269: [AMDGPU] New buffer intrinsics (authored by tpr, committed by ). · Explain WhyAug 21 2018, 4:08 AM
This revision was automatically updated to reflect the committed changes.