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Differential D49593

[AArch64][SVE] Asm: Enable instructions to be prefixed.
ClosedPublic

Authored by sdesmalen on Jul 20 2018, 2:36 AM.

Details

Reviewers
rengolin
SjoerdMeijer
samparker
fhahn
javed.absar
Commits
rGe64206a02c25: [AArch64][SVE] Asm: Enable instructions to be prefixed.
rL338261: [AArch64][SVE] Asm: Enable instructions to be prefixed.
Summary

This patch enables instructions that are destructive on their
destination- and first source operand, to be prefixed with a
MOVPRFX instruction.

This patch also adds a variety of tests:

  • positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms.
  • negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx.
  • negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly.

This is patch [2/2] in a series to add MOVPRFX instructions:

Diff Detail

Event Timeline

sdesmalen created this revision.Jul 20 2018, 2:36 AM
Herald added subscribers: rkruppe, kristof.beyls, tschuett. · View Herald TranscriptJul 20 2018, 2:36 AM
sdesmalen edited the summary of this revision. (Show Details)Jul 20 2018, 2:37 AM
sdesmalen added a parent revision: D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
sdesmalen added a comment.Jul 20 2018, 2:43 AM

It is probably worth noting that the positive and negative tests to explicitly test that instructions (and/or specific forms of those instructions) are or are not movprfx-able, are auto-generated using a separate tool (so my apologies for the large diff :)). The movprfx-diagnostics.s is worth pointing out as testing the specific rules of the MOVPRFX instruction.

sdesmalen updated this revision to Diff 157922.Jul 30 2018, 12:42 AM
  • Updated to reflect changes in D49592 to use TSFlags instead of separate table for annotating instructions as destructive operations.
  • Added negative tests for new SVE instructions that were added since uploading the previous patch.
SjoerdMeijer accepted this revision.Jul 30 2018, 6:43 AM

Looks reasonable to me.

This revision is now accepted and ready to land.Jul 30 2018, 6:43 AM
Closed by commit rL338261: [AArch64][SVE] Asm: Enable instructions to be prefixed. (authored by s.desmalen). · Explain WhyJul 30 2018, 9:06 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 157922

lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 886 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE] in {
defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">; defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">;
defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">; defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">;
defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">; defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">;
defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">; defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">;
defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">; defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">;
defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">; defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">;
def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16>; def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16, ElementSizeS>;
def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32>; def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32, ElementSizeS>;
def SCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110010, "scvtf", ZPR16, ZPR16>; def SCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110010, "scvtf", ZPR16, ZPR16, ElementSizeH>;
def SCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010100, "scvtf", ZPR32, ZPR32>; def SCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010100, "scvtf", ZPR32, ZPR32, ElementSizeS>;
def UCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010101, "ucvtf", ZPR32, ZPR32>; def UCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010101, "ucvtf", ZPR32, ZPR32, ElementSizeS>;
def UCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110011, "ucvtf", ZPR16, ZPR16>; def UCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110011, "ucvtf", ZPR16, ZPR16, ElementSizeH>;
def FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16>; def FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16, ElementSizeH>;
def FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32>; def FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32, ElementSizeS>;
def FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16>; def FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16, ElementSizeH>;
def FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32>; def FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32, ElementSizeS>;
def FCVT_ZPmZ_DtoH : sve_fp_2op_p_zd<0b1101000, "fcvt", ZPR64, ZPR16>; def FCVT_ZPmZ_DtoH : sve_fp_2op_p_zd<0b1101000, "fcvt", ZPR64, ZPR16, ElementSizeD>;
def FCVT_ZPmZ_HtoD : sve_fp_2op_p_zd<0b1101001, "fcvt", ZPR16, ZPR64>; def FCVT_ZPmZ_HtoD : sve_fp_2op_p_zd<0b1101001, "fcvt", ZPR16, ZPR64, ElementSizeD>;
def FCVT_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1101010, "fcvt", ZPR64, ZPR32>; def FCVT_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1101010, "fcvt", ZPR64, ZPR32, ElementSizeD>;
def FCVT_ZPmZ_StoD : sve_fp_2op_p_zd<0b1101011, "fcvt", ZPR32, ZPR64>; def FCVT_ZPmZ_StoD : sve_fp_2op_p_zd<0b1101011, "fcvt", ZPR32, ZPR64, ElementSizeD>;
def SCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110000, "scvtf", ZPR32, ZPR64>; def SCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110000, "scvtf", ZPR32, ZPR64, ElementSizeD>;
def UCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110001, "ucvtf", ZPR32, ZPR64>; def UCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110001, "ucvtf", ZPR32, ZPR64, ElementSizeD>;
def UCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110101, "ucvtf", ZPR32, ZPR16>; def UCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110101, "ucvtf", ZPR32, ZPR16, ElementSizeS>;
def SCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110100, "scvtf", ZPR64, ZPR32>; def SCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110100, "scvtf", ZPR64, ZPR32, ElementSizeD>;
def SCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110100, "scvtf", ZPR32, ZPR16>; def SCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110100, "scvtf", ZPR32, ZPR16, ElementSizeS>;
def SCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110110, "scvtf", ZPR64, ZPR16>; def SCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110110, "scvtf", ZPR64, ZPR16, ElementSizeD>;
def UCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110101, "ucvtf", ZPR64, ZPR32>; def UCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110101, "ucvtf", ZPR64, ZPR32, ElementSizeD>;
def UCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110111, "ucvtf", ZPR64, ZPR16>; def UCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110111, "ucvtf", ZPR64, ZPR16, ElementSizeD>;
def SCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110110, "scvtf", ZPR64, ZPR64>; def SCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110110, "scvtf", ZPR64, ZPR64, ElementSizeD>;
def UCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110111, "ucvtf", ZPR64, ZPR64>; def UCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110111, "ucvtf", ZPR64, ZPR64, ElementSizeD>;
def FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32>; def FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32, ElementSizeD>;
def FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32>; def FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32, ElementSizeD>;
def FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64>; def FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64, ElementSizeD>;
def FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32>; def FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32, ElementSizeS>;
def FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64>; def FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64, ElementSizeD>;
def FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32>; def FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32, ElementSizeS>;
def FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64>; def FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64, ElementSizeD>;
def FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64>; def FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64, ElementSizeD>;
def FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64>; def FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64, ElementSizeD>;
def FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64>; def FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64, ElementSizeD>;
defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn">; defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn">;
defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp">; defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp">;
defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm">; defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm">;
defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz">; defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz">;
defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta">; defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta">;
defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx">; defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx">;
defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti">; defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti">;
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 415 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
let Inst{21-19} = 0b101; let Inst{21-19} = 0b101;
let Inst{18-16} = opc{4-2}; let Inst{18-16} = opc{4-2};
let Inst{15-11} = 0b10000; let Inst{15-11} = 0b10000;
let Inst{10-9} = opc{1-0}; let Inst{10-9} = opc{1-0};
let Inst{8-5} = Pg; let Inst{8-5} = Pg;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_count_v<bits<5> opc, string asm> { multiclass sve_int_count_v<bits<5> opc, string asm> {
def _H : sve_int_count_v<0b01, opc, asm, ZPR16>; def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
def _S : sve_int_count_v<0b10, opc, asm, ZPR32>; def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
def _D : sve_int_count_v<0b11, opc, asm, ZPR64>; def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
let Inst{20} = opc{2}; let Inst{20} = opc{2};
let Inst{19-16} = imm4; let Inst{19-16} = imm4;
let Inst{15-12} = 0b1100; let Inst{15-12} = 0b1100;
let Inst{11-10} = opc{1-0}; let Inst{11-10} = opc{1-0};
let Inst{9-5} = pattern; let Inst{9-5} = pattern;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> { multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
def NAME : sve_int_countvlv<opc, asm, zprty>; def NAME : sve_int_countvlv<opc, asm, zprty>;
def : InstAlias<asm # "\t$Zdn, $pattern", def : InstAlias<asm # "\t$Zdn, $pattern",
(!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>; (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
def : InstAlias<asm # "\t$Zdn", def : InstAlias<asm # "\t$Zdn",
▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
bits<5> Zdn; bits<5> Zdn;
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-10} = 0b100100001110; let Inst{21-10} = 0b100100001110;
let Inst{9-5} = Rm; let Inst{9-5} = Rm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_perm_insrs<string asm> { multiclass sve_int_perm_insrs<string asm> {
def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>; def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>; def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>; def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>; def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
} }
class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty, class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
RegisterClass srcRegType> RegisterClass srcRegType>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm), : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
asm, "\t$Zdn, $Vm", asm, "\t$Zdn, $Vm",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<5> Vm; bits<5> Vm;
bits<5> Zdn; bits<5> Zdn;
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-10} = 0b110100001110; let Inst{21-10} = 0b110100001110;
let Inst{9-5} = Vm; let Inst{9-5} = Vm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_perm_insrv<string asm> { multiclass sve_int_perm_insrv<string asm> {
def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>; def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>; def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>; def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>; def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
} }
Show All 12 Lines: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
let Inst{31-21} = 0b00000101001; let Inst{31-21} = 0b00000101001;
let Inst{20-16} = imm8{7-3}; let Inst{20-16} = imm8{7-3};
let Inst{15-13} = 0b000; let Inst{15-13} = 0b000;
let Inst{12-10} = imm8{2-0}; let Inst{12-10} = imm8{2-0};
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Vector Select Group // SVE Vector Select Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty> class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm), : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = opc; let Inst{23-22} = opc;
let Inst{21-18} = 0b0000; let Inst{21-18} = 0b0000;
let Inst{17-5} = imms13; let Inst{17-5} = imms13;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DecoderMethod = "DecodeSVELogicalImmInstruction"; let DecoderMethod = "DecodeSVELogicalImmInstruction";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> { multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
def NAME : sve_int_log_imm<opc, asm>; def NAME : sve_int_log_imm<opc, asm>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>; (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-6} = 0b0000; let Inst{9-6} = 0b0000;
let Inst{5} = i1; let Inst{5} = i1;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> { multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
} }
Show All 11 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
let Inst{21-20} = 0b00; let Inst{21-20} = 0b00;
let Inst{19-16} = opc; let Inst{19-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> { multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> {
def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>; def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>; def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
} }
Show All 9 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3),
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21-19} = 0b010; let Inst{21-19} = 0b010;
let Inst{18-16} = imm3; let Inst{18-16} = imm3;
let Inst{15-10} = 0b100000; let Inst{15-10} = 0b100000;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_fp_ftmad<string asm> { multiclass sve_fp_ftmad<string asm> {
def _H : sve_fp_ftmad<0b01, asm, ZPR16>; def _H : sve_fp_ftmad<0b01, asm, ZPR16>;
def _S : sve_fp_ftmad<0b10, asm, ZPR32>; def _S : sve_fp_ftmad<0b10, asm, ZPR32>;
def _D : sve_fp_ftmad<0b11, asm, ZPR64>; def _D : sve_fp_ftmad<0b11, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15} = 0b0; let Inst{15} = 0b0;
let Inst{14-13} = opc; let Inst{14-13} = opc;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> { multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> {
def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>; def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>;
def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>; def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>;
def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>; def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>;
} }
Show All 13 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
let Inst{20-16} = Za; let Inst{20-16} = Za;
let Inst{15} = 0b1; let Inst{15} = 0b1;
let Inst{14-13} = opc; let Inst{14-13} = opc;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> { multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> {
def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>; def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>;
def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>; def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>;
def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>; def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>;
} }
Show All 12 Lines: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21} = 0b1; let Inst{21} = 0b1;
let Inst{15-11} = 0; let Inst{15-11} = 0;
let Inst{10} = opc; let Inst{10} = opc;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> { multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> {
def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> { def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> {
bits<3> Zm; bits<3> Zm;
bits<3> iop; bits<3> iop;
let Inst{22} = iop{2}; let Inst{22} = iop{2};
let Inst{20-19} = iop{1-0}; let Inst{20-19} = iop{1-0};
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15} = 0; let Inst{15} = 0;
let Inst{14-13} = imm; let Inst{14-13} = imm;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_fcmla<string asm> { multiclass sve_fp_fcmla<string asm> {
def _H : sve_fp_fcmla<0b01, asm, ZPR16>; def _H : sve_fp_fcmla<0b01, asm, ZPR16>;
def _S : sve_fp_fcmla<0b10, asm, ZPR32>; def _S : sve_fp_fcmla<0b10, asm, ZPR32>;
def _D : sve_fp_fcmla<0b11, asm, ZPR64>; def _D : sve_fp_fcmla<0b11, asm, ZPR64>;
} }
Show All 15 Lines: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21} = 0b1; let Inst{21} = 0b1;
let Inst{15-12} = 0b0001; let Inst{15-12} = 0b0001;
let Inst{11-10} = imm; let Inst{11-10} = imm;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_fp_fcmla_by_indexed_elem<string asm> { multiclass sve_fp_fcmla_by_indexed_elem<string asm> {
def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> { def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> {
bits<3> Zm; bits<3> Zm;
bits<2> iop; bits<2> iop;
let Inst{20-19} = iop; let Inst{20-19} = iop;
let Inst{18-16} = Zm; let Inst{18-16} = Zm;
Show All 25 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
let Inst{21-17} = 0; let Inst{21-17} = 0;
let Inst{16} = imm; let Inst{16} = imm;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_fp_fcadd<string asm> { multiclass sve_fp_fcadd<string asm> {
def _H : sve_fp_fcadd<0b01, asm, ZPR16>; def _H : sve_fp_fcadd<0b01, asm, ZPR16>;
def _S : sve_fp_fcadd<0b10, asm, ZPR32>; def _S : sve_fp_fcadd<0b10, asm, ZPR32>;
def _D : sve_fp_fcadd<0b11, asm, ZPR64>; def _D : sve_fp_fcadd<0b11, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesmulticlass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>; def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Unary Operations Group // SVE Floating Point Unary Operations Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype, class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
RegisterOperand o_zprtype> RegisterOperand o_zprtype, ElementSizeEnum size>
: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn), : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
asm, "\t$Zd, $Pg/m, $Zn", asm, "\t$Zd, $Pg/m, $Zn",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<3> Pg; bits<3> Pg;
bits<5> Zd; bits<5> Zd;
bits<5> Zn; bits<5> Zn;
let Inst{31-24} = 0b01100101; let Inst{31-24} = 0b01100101;
let Inst{23-22} = opc{6-5}; let Inst{23-22} = opc{6-5};
let Inst{21} = 0b0; let Inst{21} = 0b0;
let Inst{20-16} = opc{4-0}; let Inst{20-16} = opc{4-0};
let Inst{15-13} = 0b101; let Inst{15-13} = 0b101;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = size;
} }
multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> { multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> {
def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16>; def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>;
def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32>; def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>;
def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64>; def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Unary Operations - Unpredicated Group // SVE Floating Point Unary Operations - Unpredicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm, class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm,
ZPRRegOp zprty> ZPRRegOp zprty>
Show All 35 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
let Inst{20-19} = fmt; let Inst{20-19} = fmt;
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-13} = 0b000; let Inst{15-13} = 0b000;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_bin_pred_log<bits<3> opc, string asm> { multiclass sve_int_bin_pred_log<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15-14} = 0b11; let Inst{15-14} = 0b11;
let Inst{13} = opc; let Inst{13} = opc;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Za; let Inst{9-5} = Za;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> { multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> {
def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>; def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>;
def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>; def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>;
def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>; def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>;
def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>; def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>;
} }
Show All 14 Lines: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15-14} = 0b01; let Inst{15-14} = 0b01;
let Inst{13} = opc; let Inst{13} = opc;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> { multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> {
def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>; def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>;
def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>; def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>;
def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>; def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>;
def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>; def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>;
} }
Show All 14 Lines: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm,
let Inst{21} = 0; let Inst{21} = 0;
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15-11} = 0; let Inst{15-11} = 0;
let Inst{10} = U; let Inst{10} = U;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = zprty1.ElementSize;
} }
multiclass sve_intx_dot<bit opc, string asm> { multiclass sve_intx_dot<bit opc, string asm> {
def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>; def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>;
def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>; def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 12 Lines: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
let Inst{22} = sz; let Inst{22} = sz;
let Inst{21} = 0b1; let Inst{21} = 0b1;
let Inst{15-11} = 0; let Inst{15-11} = 0;
let Inst{10} = U; let Inst{10} = U;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> { multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> {
def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
bits<2> iop; bits<2> iop;
bits<3> Zm; bits<3> Zm;
let Inst{20-19} = iop; let Inst{20-19} = iop;
let Inst{18-16} = Zm; let Inst{18-16} = Zm;
Show All 25 Lines: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
let Inst{19} = opc{0}; let Inst{19} = opc{0};
let Inst{18-16} = opc{3-1}; let Inst{18-16} = opc{3-1};
let Inst{15-13} = 0b101; let Inst{15-13} = 0b101;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> { multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> {
def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>; def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
let Inst{21-19} = 0b100; let Inst{21-19} = 0b100;
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-14} = 0b11; let Inst{15-14} = 0b11;
let Inst{13} = imm{8}; // sh let Inst{13} = imm{8}; // sh
let Inst{12-5} = imm{7-0}; // imm8 let Inst{12-5} = imm{7-0}; // imm8
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_arith_imm0<bits<3> opc, string asm> { multiclass sve_int_arith_imm0<bits<3> opc, string asm> {
def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>; def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>; def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>; def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
} }
Show All 9 Lines: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
let Inst{31-24} = 0b00100101; let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-16} = opc; let Inst{21-16} = opc;
let Inst{15-13} = 0b110; let Inst{15-13} = 0b110;
let Inst{12-5} = imm; let Inst{12-5} = imm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> { multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> {
def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>; def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>;
def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>; def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>;
def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>; def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>;
def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>; def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>;
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8),
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
let Inst{19-16} = Pg; let Inst{19-16} = Pg;
let Inst{15-13} = 0b110; let Inst{15-13} = 0b110;
let Inst{12-5} = imm8; let Inst{12-5} = imm8;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_dup_fpimm_pred<string asm> { multiclass sve_int_dup_fpimm_pred<string asm> {
def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>; def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>;
def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>; def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>;
def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>; def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>;
def : InstAlias<"fmov $Zd, $Pg/m, $imm8", def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
Show All 16 Lines: I<(outs zprty:$Zd), iops,
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
let Inst{19-16} = Pg; let Inst{19-16} = Pg;
let Inst{15} = 0b0; let Inst{15} = 0b0;
let Inst{14} = m; let Inst{14} = m;
let Inst{13} = imm{8}; // sh let Inst{13} = imm{8}; // sh
let Inst{12-5} = imm{7-0}; // imm8 let Inst{12-5} = imm{7-0}; // imm8
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_dup_imm_pred_merge<string asm> { multiclass sve_int_dup_imm_pred_merge<string asm> {
let Constraints = "$Zd = $_Zd" in { let Constraints = "$Zd = $_Zd" in {
def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
▲ Show 20 Lines • Show All 438 Lines • ▼ Show 20 Linesmulticlass sve_int_index_rr<string asm> {
def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>; def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>; def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
} }
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Bitwise Shift - Predicated Group // SVE Bitwise Shift - Predicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm,
ZPRRegOp zprty, Operand immtype> ZPRRegOp zprty, Operand immtype,
ElementSizeEnum size>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<3> Pg; bits<3> Pg;
bits<5> Zdn; bits<5> Zdn;
bits<6> imm; bits<6> imm;
let Inst{31-24} = 0b00000100; let Inst{31-24} = 0b00000100;
let Inst{23-22} = tsz8_64{3-2}; let Inst{23-22} = tsz8_64{3-2};
let Inst{21-19} = 0b000; let Inst{21-19} = 0b000;
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-8} = tsz8_64{1-0}; let Inst{9-8} = tsz8_64{1-0};
let Inst{7-5} = imm{2-0}; // imm3 let Inst{7-5} = imm{2-0}; // imm3
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = size;
} }
multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8,
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { ElementSizeB>;
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16,
ElementSizeH> {
let Inst{8} = imm{3}; let Inst{8} = imm{3};
} }
def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32,
ElementSizeS> {
let Inst{9-8} = imm{4-3}; let Inst{9-8} = imm{4-3};
} }
def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64,
ElementSizeD> {
let Inst{22} = imm{5}; let Inst{22} = imm{5};
let Inst{9-8} = imm{4-3}; let Inst{9-8} = imm{4-3};
} }
} }
multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> { multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8,
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { ElementSizeB>;
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16,
ElementSizeH> {
let Inst{8} = imm{3}; let Inst{8} = imm{3};
} }
def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32,
ElementSizeS> {
let Inst{9-8} = imm{4-3}; let Inst{9-8} = imm{4-3};
} }
def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64,
ElementSizeD> {
let Inst{22} = imm{5}; let Inst{22} = imm{5};
let Inst{9-8} = imm{4-3}; let Inst{9-8} = imm{4-3};
} }
} }
class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc, class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
string asm, ZPRRegOp zprty, ZPRRegOp zprty2> string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
Show All 9 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
let Inst{19} = wide; let Inst{19} = wide;
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> { multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>;
def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>;
def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>;
def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>;
} }
▲ Show 20 Lines • Show All 618 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
let Inst{21-17} = 0b10100; let Inst{21-17} = 0b10100;
let Inst{16} = ab; let Inst{16} = ab;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_perm_clast_zz<bit ab, string asm> { multiclass sve_int_perm_clast_zz<bit ab, string asm> {
def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>; def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>;
def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>; def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>;
def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>; def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>;
def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>; def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>;
} }
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b101100100; let Inst{21-13} = 0b101100100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_int_perm_splice<string asm> { multiclass sve_int_perm_splice<string asm> {
def _B : sve_int_perm_splice<0b00, asm, ZPR8>; def _B : sve_int_perm_splice<0b00, asm, ZPR8>;
def _H : sve_int_perm_splice<0b01, asm, ZPR16>; def _H : sve_int_perm_splice<0b01, asm, ZPR16>;
def _S : sve_int_perm_splice<0b10, asm, ZPR32>; def _S : sve_int_perm_splice<0b10, asm, ZPR32>;
def _D : sve_int_perm_splice<0b11, asm, ZPR64>; def _D : sve_int_perm_splice<0b11, asm, ZPR64>;
} }
Show All 12 Lines: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
let Inst{21-18} = 0b1001; let Inst{21-18} = 0b1001;
let Inst{17-16} = opc; let Inst{17-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_perm_rev_rbit<string asm> { multiclass sve_int_perm_rev_rbit<string asm> {
def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>; def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>;
def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>; def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>;
def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>; def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>;
def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>; def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>;
} }
Show All 25 Lines: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b101000101; let Inst{21-13} = 0b101000101;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Rn; let Inst{9-5} = Rn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_perm_cpy_r<string asm> { multiclass sve_int_perm_cpy_r<string asm> {
def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>; def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>; def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>; def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>; def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
Show All 19 Lines: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
let Inst{31-24} = 0b00000101; let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b100000100; let Inst{21-13} = 0b100000100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Vn; let Inst{9-5} = Vn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd"; let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_perm_cpy_v<string asm> { multiclass sve_int_perm_cpy_v<string asm> {
def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>; def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>; def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>; def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>; def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
▲ Show 20 Lines • Show All 921 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zd), iops,
let Inst{31-24} = 0b00000100; let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz8_32; let Inst{23-22} = sz8_32;
let Inst{21-19} = 0b010; let Inst{21-19} = 0b010;
let Inst{18-16} = opc; let Inst{18-16} = opc;
let Inst{15-13} = 0b001; let Inst{15-13} = 0b001;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
let ElementSize = zprty.ElementSize;
} }
multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> { multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
let Constraints = "$Zd = $_Zd" in { let Constraints = "$Zd = $_Zd" in {
def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m", def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
(ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>; (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m", def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
(ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>; (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

test/MC/AArch64/SVE/abs.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 96 04 <unknown> // CHECK-UNKNOWN: ff bf 96 04 <unknown>
abs z31.d, p7/m, z31.d abs z31.d, p7/m, z31.d
// CHECK-INST: abs z31.d, p7/m, z31.d // CHECK-INST: abs z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd6,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d6 04 <unknown> // CHECK-UNKNOWN: ff bf d6 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
abs z4.d, p7/m, z31.d
// CHECK-INST: abs z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d6 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
abs z4.d, p7/m, z31.d
// CHECK-INST: abs z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d6 04 <unknown>

test/MC/AArch64/SVE/add-diagnostics.s

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: add z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: add z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z0.d, z0.d, #65536 add z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: add z0.d, z0.d, #65536 // CHECK-NEXT: add z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
add z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: add z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.s, p0/z, z30.s
add z23.s, z13.s, z8.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: add z23.s, z13.s, z8.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
add z23.s, z13.s, z8.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: add z23.s, z13.s, z8.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/add.s

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
// CHECK-UNKNOWN: ff ff e0 25 <unknown> // CHECK-UNKNOWN: ff ff e0 25 <unknown>
add z31.d, z31.d, #65280 add z31.d, z31.d, #65280
// CHECK-INST: add z31.d, z31.d, #65280 // CHECK-INST: add z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe0,0x25] // CHECK-ENCODING: [0xff,0xff,0xe0,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e0 25 <unknown> // CHECK-UNKNOWN: ff ff e0 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.b, p7/z, z6.b
// CHECK-INST: movprfx z4.b, p7/z, z6.b
// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 10 04 <unknown>
add z4.b, p7/m, z4.b, z31.b
// CHECK-INST: add z4.b, p7/m, z4.b, z31.b
// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f 00 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
add z4.b, p7/m, z4.b, z31.b
// CHECK-INST: add z4.b, p7/m, z4.b, z31.b
// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f 00 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
add z31.d, z31.d, #65280
// CHECK-INST: add z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe0,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e0 25 <unknown>

test/MC/AArch64/SVE/adr-diagnostics.s

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, uxtw #4] // CHECK-NEXT: adr z0.d, [z0.d, z0.d, uxtw #4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
adr z0.d, [z0.d, z0.d, sxtw #4] adr z0.d, [z0.d, z0.d, sxtw #4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4] // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
adr z0.d, [z0.d, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
adr z0.d, [z0.d, z0.d, sxtw #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/and-diagnostics.s

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Operation only has zeroing predicate behaviour (p0/z). // Operation only has zeroing predicate behaviour (p0/z).
and p0.b, p0/m, p1.b, p2.b and p0.b, p0/m, p1.b, p2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b // CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
and z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: and z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.d, p0/z, z30.d
and z23.d, z13.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: and z23.d, z13.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
and z23.d, z13.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: and z23.d, z13.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/and.s

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 00 25 <unknown> // CHECK-UNKNOWN: 00 40 00 25 <unknown>
and p15.b, p15/z, p15.b, p15.b and p15.b, p15/z, p15.b, p15.b
// CHECK-INST: mov p15.b, p15/z, p15.b // CHECK-INST: mov p15.b, p15/z, p15.b
// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 7d 0f 25 <unknown> // CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
and z4.d, p7/m, z4.d, z31.d
// CHECK-INST: and z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f da 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
and z4.d, p7/m, z4.d, z31.d
// CHECK-INST: and z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f da 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
and z0.d, z0.d, #0x6
// CHECK-INST: and z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 83 05 <unknown>

test/MC/AArch64/SVE/andv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
andv h0, p8, z31.h andv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: andv h0, p8, z31.h // CHECK-NEXT: andv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
andv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: andv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
andv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: andv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/asr-diagnostics.s

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
asr z0.b, p8/m, z0.b, z1.b asr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
asr z31.d, z31.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: asr z31.d, z31.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
asr z31.d, z31.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: asr z31.d, z31.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
asr z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: asr z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
asr z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: asr z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/asr.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 62 04 <unknown> // CHECK-UNKNOWN: 20 80 62 04 <unknown>
asr z0.s, z1.s, z2.d asr z0.s, z1.s, z2.d
// CHECK-INST: asr z0.s, z1.s, z2.d // CHECK-INST: asr z0.s, z1.s, z2.d
// CHECK-ENCODING: [0x20,0x80,0xa2,0x04] // CHECK-ENCODING: [0x20,0x80,0xa2,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 a2 04 <unknown> // CHECK-UNKNOWN: 20 80 a2 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
asr z31.d, p0/m, z31.d, #64
// CHECK-INST: asr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x80,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 80 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
asr z31.d, p0/m, z31.d, #64
// CHECK-INST: asr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x80,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 80 04 <unknown>
movprfx z0.s, p0/z, z7.s
// CHECK-INST: movprfx z0.s, p0/z, z7.s
// CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 90 04 <unknown>
asr z0.s, p0/m, z0.s, z1.d
// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x98,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 98 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
asr z0.s, p0/m, z0.s, z1.d
// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x98,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 98 04 <unknown>

test/MC/AArch64/SVE/asrd.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 83 c4 04 <unknown> // CHECK-UNKNOWN: e0 83 c4 04 <unknown>
asrd z31.d, p0/m, z31.d, #64 asrd z31.d, p0/m, z31.d, #64
// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 // CHECK-INST: asrd z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] // CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 84 04 <unknown> // CHECK-UNKNOWN: 1f 80 84 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
asrd z31.d, p0/m, z31.d, #64
// CHECK-INST: asrd z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 84 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
asrd z31.d, p0/m, z31.d, #64
// CHECK-INST: asrd z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 84 04 <unknown>

test/MC/AArch64/SVE/asrr.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 94 04 <unknown> // CHECK-UNKNOWN: 00 80 94 04 <unknown>
asrr z0.d, p0/m, z0.d, z0.d asrr z0.d, p0/m, z0.d, z0.d
// CHECK-INST: asrr z0.d, p0/m, z0.d, z0.d // CHECK-INST: asrr z0.d, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x80,0xd4,0x04] // CHECK-ENCODING: [0x00,0x80,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 d4 04 <unknown> // CHECK-UNKNOWN: 00 80 d4 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
asrr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d4 04 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
asrr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d4 04 <unknown>

test/MC/AArch64/SVE/bic-diagnostics.s

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// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Operation only has zeroing predicate behaviour (p0/z). // Operation only has zeroing predicate behaviour (p0/z).
bic p0.b, p0/m, p1.b, p2.b bic p0.b, p0/m, p1.b, p2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b // CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bic z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bic z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.d, p0/z, z30.d
bic z23.d, z13.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bic z23.d, z13.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
bic z23.d, z13.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bic z23.d, z13.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/bic.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7d 0f 25 <unknown> // CHECK-UNKNOWN: ff 7d 0f 25 <unknown>
bic p0.b, p0/z, p0.b, p0.b bic p0.b, p0/z, p0.b, p0.b
// CHECK-INST: bic p0.b, p0/z, p0.b, p0.b // CHECK-INST: bic p0.b, p0/z, p0.b, p0.b
// CHECK-ENCODING: [0x10,0x40,0x00,0x25] // CHECK-ENCODING: [0x10,0x40,0x00,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 10 40 00 25 <unknown> // CHECK-UNKNOWN: 10 40 00 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
bic z4.d, p7/m, z4.d, z31.d
// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f db 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
bic z4.d, p7/m, z4.d, z31.d
// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f db 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
bic z0.d, z0.d, #0x6
// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 83 05 <unknown>

test/MC/AArch64/SVE/clasta-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: clasta z0.s, p7, z0.s, z31.d // CHECK-NEXT: clasta z0.s, p7, z0.s, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
clasta z0.d, p7, z0.d, z31.b clasta z0.d, p7, z0.d, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: clasta z0.d, p7, z0.d, z31.b // CHECK-NEXT: clasta z0.d, p7, z0.d, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
clasta x0, p7, x0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clasta x0, p7, x0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
clasta x0, p7, x0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clasta x0, p7, x0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p7/z, z6.d
clasta d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clasta d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
clasta d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clasta d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p7/z, z7.d
clasta z0.d, p7, z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: clasta z0.d, p7, z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/clasta.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a8 05 <unknown> // CHECK-UNKNOWN: e0 9f a8 05 <unknown>
clasta z0.d, p7, z0.d, z31.d clasta z0.d, p7, z0.d, z31.d
// CHECK-INST: clasta z0.d, p7, z0.d, z31.d // CHECK-INST: clasta z0.d, p7, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e8 05 <unknown> // CHECK-UNKNOWN: e0 9f e8 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
clasta z0.d, p7, z0.d, z31.d
// CHECK-INST: clasta z0.d, p7, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e8 05 <unknown>

test/MC/AArch64/SVE/clastb-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: clastb z0.s, p7, z0.s, z31.d // CHECK-NEXT: clastb z0.s, p7, z0.s, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
clastb z0.d, p7, z0.d, z31.b clastb z0.d, p7, z0.d, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: clastb z0.d, p7, z0.d, z31.b // CHECK-NEXT: clastb z0.d, p7, z0.d, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
clastb x0, p7, x0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clastb x0, p7, x0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
clastb x0, p7, x0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clastb x0, p7, x0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p7/z, z6.d
clastb d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clastb d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
clastb d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: clastb d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p7/z, z7.d
clastb z0.d, p7, z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: clastb z0.d, p7, z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/clastb.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a9 05 <unknown> // CHECK-UNKNOWN: e0 9f a9 05 <unknown>
clastb z0.d, p7, z0.d, z31.d clastb z0.d, p7, z0.d, z31.d
// CHECK-INST: clastb z0.d, p7, z0.d, z31.d // CHECK-INST: clastb z0.d, p7, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e9 05 <unknown> // CHECK-UNKNOWN: e0 9f e9 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
clastb z0.d, p7, z0.d, z31.d
// CHECK-INST: clastb z0.d, p7, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e9 05 <unknown>

test/MC/AArch64/SVE/cls.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 98 04 <unknown> // CHECK-UNKNOWN: ff bf 98 04 <unknown>
cls z31.d, p7/m, z31.d cls z31.d, p7/m, z31.d
// CHECK-INST: cls z31.d, p7/m, z31.d // CHECK-INST: cls z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd8,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d8 04 <unknown> // CHECK-UNKNOWN: ff bf d8 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
cls z4.d, p7/m, z31.d
// CHECK-INST: cls z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d8 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cls z4.d, p7/m, z31.d
// CHECK-INST: cls z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d8 04 <unknown>

test/MC/AArch64/SVE/clz.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 99 04 <unknown> // CHECK-UNKNOWN: ff bf 99 04 <unknown>
clz z31.d, p7/m, z31.d clz z31.d, p7/m, z31.d
// CHECK-INST: clz z31.d, p7/m, z31.d // CHECK-INST: clz z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd9,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd9,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d9 04 <unknown> // CHECK-UNKNOWN: ff bf d9 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
clz z4.d, p7/m, z31.d
// CHECK-INST: clz z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d9 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
clz z4.d, p7/m, z31.d
// CHECK-INST: clz z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d9 04 <unknown>

test/MC/AArch64/SVE/cmpeq-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmpeq p0.s, p0/z, z0.s, #16 cmpeq p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmpeq p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpeq p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmpeq p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpeq p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmpge-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmpge p0.s, p0/z, z0.s, #16 cmpge p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmpge p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpge p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmpge p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpge p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmpgt-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmpgt p0.s, p0/z, z0.s, #16 cmpgt p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmpgt p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpgt p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmpgt p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpgt p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmphi-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #-1 // CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmphi p0.s, p0/z, z0.s, #128 cmphi p0.s, p0/z, z0.s, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #128 // CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmphi p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmphi p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmphi p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmphi p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmphs-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #-1 // CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmphs p0.s, p0/z, z0.s, #128 cmphs p0.s, p0/z, z0.s, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #128 // CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmphs p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmphs p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmphs p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmphs p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmple-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmple p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmple p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmple p0.s, p0/z, z0.s, #16 cmple p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmple p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmple p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmple p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmple p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmple p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmple p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmplo-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #-1 // CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmplo p0.s, p0/z, z0.s, #128 cmplo p0.s, p0/z, z0.s, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #128 // CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmplo p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmplo p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmplo p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmplo p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmpls-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #-1 // CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmpls p0.s, p0/z, z0.s, #128 cmpls p0.s, p0/z, z0.s, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127].
// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #128 // CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmpls p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpls p0.d, p0/z, z0.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmpls p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpls p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmplt-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmplt p0.s, p0/z, z0.s, #16 cmplt p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmplt p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmplt p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmplt p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmplt p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cmpne-diagnostics.s

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #-17 // CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #-17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmpne p0.s, p0/z, z0.s, #16 cmpne p0.s, p0/z, z0.s, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #16 // CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cmpne p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpne p0.d, p0/z, z0.d, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmpne p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
cmpne p0.s, p0/z, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cnot.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 9b 04 <unknown> // CHECK-UNKNOWN: ff bf 9b 04 <unknown>
cnot z31.d, p7/m, z31.d cnot z31.d, p7/m, z31.d
// CHECK-INST: cnot z31.d, p7/m, z31.d // CHECK-INST: cnot z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xdb,0x04] // CHECK-ENCODING: [0xff,0xbf,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf db 04 <unknown> // CHECK-UNKNOWN: ff bf db 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
cnot z4.d, p7/m, z31.d
// CHECK-INST: cnot z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf db 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cnot z4.d, p7/m, z31.d
// CHECK-INST: cnot z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf db 04 <unknown>

test/MC/AArch64/SVE/cnt.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 9a 04 <unknown> // CHECK-UNKNOWN: ff bf 9a 04 <unknown>
cnt z31.d, p7/m, z31.d cnt z31.d, p7/m, z31.d
// CHECK-INST: cnt z31.d, p7/m, z31.d // CHECK-INST: cnt z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xda,0x04] // CHECK-ENCODING: [0xff,0xbf,0xda,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf da 04 <unknown> // CHECK-UNKNOWN: ff bf da 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
cnt z4.d, p7/m, z31.d
// CHECK-INST: cnt z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf da 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cnt z4.d, p7/m, z31.d
// CHECK-INST: cnt z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf da 04 <unknown>

test/MC/AArch64/SVE/compact-diagnostics.s

Show All 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: compact z31.b, p7, z31.b // CHECK-NEXT: compact z31.b, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
compact z31.h, p7, z31.h compact z31.h, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: compact z31.h, p7, z31.h // CHECK-NEXT: compact z31.h, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
compact z31.d, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: compact z31.d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
compact z31.d, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: compact z31.d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/cpy.s

Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 50 df 05 <unknown> // CHECK-UNKNOWN: 15 50 df 05 <unknown>
cpy z21.d, p15/m, #-128, lsl #8 cpy z21.d, p15/m, #-128, lsl #8
// CHECK-INST: mov z21.d, p15/m, #-32768 // CHECK-INST: mov z21.d, p15/m, #-32768
// CHECK-ENCODING: [0x15,0x70,0xdf,0x05] // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 70 df 05 <unknown> // CHECK-UNKNOWN: 15 70 df 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
cpy z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
cpy z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
movprfx z21.d, p7/z, z28.d
// CHECK-INST: movprfx z21.d, p7/z, z28.d
// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 3f d0 04 <unknown>
cpy z21.d, p7/m, #-128, lsl #8
// CHECK-INST: mov z21.d, p7/m, #-32768
// CHECK-ENCODING: [0x15,0x70,0xd7,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 70 d7 05 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
cpy z21.d, p15/m, #-128, lsl #8
// CHECK-INST: mov z21.d, p15/m, #-32768
// CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 70 df 05 <unknown>
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
cpy z4.d, p7/m, d31
// CHECK-INST: mov z4.d, p7/m, d31
// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cpy z4.d, p7/m, d31
// CHECK-INST: mov z4.d, p7/m, d31
// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f e0 05 <unknown>

test/MC/AArch64/SVE/decp-diagnostics.s

Show All 30 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: decp x0, p0/m // CHECK-NEXT: decp x0, p0/m
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
decp x0, p0.q decp x0, p0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: decp x0, p0.q // CHECK-NEXT: decp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
decp z31.d, p7
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: decp z31.d, p7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/decp.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown> // CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.d, p15 decp z31.d, p15
// CHECK-INST: decp z31.d, p15 // CHECK-INST: decp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xed,0x25] // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown> // CHECK-UNKNOWN: ff 81 ed 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
decp z31.d, p15
// CHECK-INST: decp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>

test/MC/AArch64/SVE/dup-diagnostics.s

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: dup z22.q, z7.q[-1] // CHECK-NEXT: dup z22.q, z7.q[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
dup z24.q, z21.q[4] dup z24.q, z21.q[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: dup z24.q, z21.q[4] // CHECK-NEXT: dup z24.q, z21.q[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b
dup z31.b, wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z31.b, wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
dup z31.b, wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z31.b, wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21.d, p0/z, z28.d
dup z21.d, #32512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z21.d, #32512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
dup z21.d, #32512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z21.d, #32512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
dup z31.d, z31.d[7]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z31.d, z31.d[7]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
dup z31.d, z31.d[7]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dup z31.d, z31.d[7]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/dupm-diagnostics.s

Show All 31 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: dupm z5.s, #0xffffffffffffff9 // CHECK-NEXT: dupm z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
dupm z15.d, #0xfffffffffffffffa dupm z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: dupm z15.d, #0xfffffffffffffffa // CHECK-NEXT: dupm z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
dupm z0.d, #0xfffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
dupm z0.d, #0xfffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/eon-diagnostics.s

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eon z7.d, z8.d, #254 // CHECK-NEXT: eon z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z7.d, z8.d, #254 eon z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eon z7.d, z8.d, #254 // CHECK-NEXT: eon z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eon z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eon z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/eon.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 40 05 <unknown> // CHECK-UNKNOWN: a0 eb 40 05 <unknown>
eon z0.d, z0.d, #0x6 eon z0.d, z0.d, #0x6
// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x43,0x05] // CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 43 05 <unknown> // CHECK-UNKNOWN: a0 ef 43 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
eon z0.d, z0.d, #0x6
// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 43 05 <unknown>

test/MC/AArch64/SVE/eor-diagnostics.s

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Operation only has zeroing predicate behaviour (p0/z). // Operation only has zeroing predicate behaviour (p0/z).
eor p0.b, p0/m, p1.b, p2.b eor p0.b, p0/m, p1.b, p2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b // CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eor z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eor z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
eor z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: eor z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
eor z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: eor z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/eor.s

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 42 00 25 <unknown> // CHECK-UNKNOWN: 00 42 00 25 <unknown>
eor p15.b, p15/z, p15.b, p15.b eor p15.b, p15/z, p15.b, p15.b
// CHECK-INST: not p15.b, p15/z, p15.b // CHECK-INST: not p15.b, p15/z, p15.b
// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 7f 0f 25 <unknown> // CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.b, p7/z, z6.b
// CHECK-INST: movprfx z4.b, p7/z, z6.b
// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 10 04 <unknown>
eor z4.b, p7/m, z4.b, z31.b
// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b
// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f 19 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
eor z4.b, p7/m, z4.b, z31.b
// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b
// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f 19 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
eor z0.d, z0.d, #0x6
// CHECK-INST: eor z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 43 05 <unknown>

test/MC/AArch64/SVE/eorv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
eorv h0, p8, z31.h eorv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: eorv h0, p8, z31.h // CHECK-NEXT: eorv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
eorv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: eorv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
eorv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: eorv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ext-diagnostics.s

Show All 25 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, z0.b, z1.b, #-1 // CHECK-NEXT: ext z0.b, z0.b, z1.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, z0.b, z1.b, #256 ext z0.b, z0.b, z1.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, z0.b, z1.b, #256 // CHECK-NEXT: ext z0.b, z0.b, z1.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b
ext z31.b, z31.b, z0.b, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: ext z31.b, z31.b, z0.b, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ext.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 00 20 05 <unknown> // CHECK-UNKNOWN: 1f 00 20 05 <unknown>
ext z31.b, z31.b, z0.b, #255 ext z31.b, z31.b, z0.b, #255
// CHECK-INST: ext z31.b, z31.b, z0.b, #255 // CHECK-INST: ext z31.b, z31.b, z0.b, #255
// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown> // CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
ext z31.b, z31.b, z0.b, #255
// CHECK-INST: ext z31.b, z31.b, z0.b, #255
// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>

test/MC/AArch64/SVE/fabd.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 88 65 <unknown> // CHECK-UNKNOWN: e0 9f 88 65 <unknown>
fabd z0.d, p7/m, z0.d, z31.d fabd z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c8 65 <unknown> // CHECK-UNKNOWN: e0 9f c8 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fabd z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c8 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fabd z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c8 65 <unknown>

test/MC/AArch64/SVE/fabs.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 9c 04 <unknown> // CHECK-UNKNOWN: ff bf 9c 04 <unknown>
fabs z31.d, p7/m, z31.d fabs z31.d, p7/m, z31.d
// CHECK-INST: fabs z31.d, p7/m, z31.d // CHECK-INST: fabs z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xdc,0x04] // CHECK-ENCODING: [0xff,0xbf,0xdc,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf dc 04 <unknown> // CHECK-UNKNOWN: ff bf dc 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
fabs z4.d, p7/m, z31.d
// CHECK-INST: fabs z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf dc 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
fabs z4.d, p7/m, z31.d
// CHECK-INST: fabs z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf dc 04 <unknown>

test/MC/AArch64/SVE/facge-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
facge p0.b, p0/z, z0.b, z0.b facge p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: facge p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: facge p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
facge p0.b, p0/z, z0.b, #0.0 facge p0.b, p0/z, z0.b, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
// CHECK-NEXT: facge p0.b, p0/z, z0.b, #0.0 // CHECK-NEXT: facge p0.b, p0/z, z0.b, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
facge p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
facge p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/facgt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
facgt p0.b, p0/z, z0.b, z0.b facgt p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: facgt p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: facgt p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
facgt p0.b, p0/z, z0.b, #0.0 facgt p0.b, p0/z, z0.b, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
// CHECK-NEXT: facgt p0.b, p0/z, z0.b, #0.0 // CHECK-NEXT: facgt p0.b, p0/z, z0.b, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
facgt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
facgt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/facle-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
facle p0.b, p0/z, z0.b, z0.b facle p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: facle p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: facle p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
facle p0.b, p0/z, z0.b, #0.0 facle p0.b, p0/z, z0.b, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
// CHECK-NEXT: facle p0.b, p0/z, z0.b, #0.0 // CHECK-NEXT: facle p0.b, p0/z, z0.b, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
facle p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
facle p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/faclt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
faclt p0.b, p0/z, z0.b, z0.b faclt p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: faclt p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: faclt p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
faclt p0.b, p0/z, z0.b, #0.0 faclt p0.b, p0/z, z0.b, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
// CHECK-NEXT: faclt p0.b, p0/z, z0.b, #0.0 // CHECK-NEXT: faclt p0.b, p0/z, z0.b, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
faclt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
faclt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fadd-diagnostics.s

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fadd z0.h, p8/m, z0.h, z31.h fadd z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fadd z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fadd z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fadd z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fadd z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fadd.s

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 9f 65 <unknown> // CHECK-UNKNOWN: 20 00 9f 65 <unknown>
fadd z0.d, z1.d, z31.d fadd z0.d, z1.d, z31.d
// CHECK-INST: fadd z0.d, z1.d, z31.d // CHECK-INST: fadd z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x00,0xdf,0x65] // CHECK-ENCODING: [0x20,0x00,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 df 65 <unknown> // CHECK-UNKNOWN: 20 00 df 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fadd z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fadd z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fadd z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c0 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fadd z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c0 65 <unknown>

test/MC/AArch64/SVE/fadda-diagnostics.s

Show All 12 Lines
fadda h0, p8, h0, z31.h fadda h0, p8, h0, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fadda h0, p8, h0, z31.h // CHECK-NEXT: fadda h0, p8, h0, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fadda v0.8h, p7, v0.8h, z31.h fadda v0.8h, p7, v0.8h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h // CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
fadda d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fadda d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fadda d0, p7, d0, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fadda d0, p7, d0, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/faddv-diagnostics.s

Show All 11 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
faddv v0, p7, z31.h faddv v0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: faddv v0, p7, z31.h // CHECK-NEXT: faddv v0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
faddv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: faddv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
faddv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: faddv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcadd.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 81 64 <unknown> // CHECK-UNKNOWN: ff 9f 81 64 <unknown>
fcadd z31.d, p7/m, z31.d, z31.d, #270 fcadd z31.d, p7/m, z31.d, z31.d, #270
// CHECK-INST: fcadd z31.d, p7/m, z31.d, z31.d, #270 // CHECK-INST: fcadd z31.d, p7/m, z31.d, z31.d, #270
// CHECK-ENCODING: [0xff,0x9f,0xc1,0x64] // CHECK-ENCODING: [0xff,0x9f,0xc1,0x64]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f c1 64 <unknown> // CHECK-UNKNOWN: ff 9f c1 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
fcadd z4.d, p7/m, z4.d, z31.d, #270
// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f c1 64 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
fcadd z4.d, p7/m, z4.d, z31.d, #270
// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f c1 64 <unknown>

test/MC/AArch64/SVE/fcmeq-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmeq p0.b, p0/z, z0.b, z0.b fcmeq p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmeq p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmeq p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmeq p0.s, p0/z, z0.s, #1.0 fcmeq p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmeq p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmeq p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmeq p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmeq p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmge-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmge p0.b, p0/z, z0.b, z0.b fcmge p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmge p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmge p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmge p0.s, p0/z, z0.s, #1.0 fcmge p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmge p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmge p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmge p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmge p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmge p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmge p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmgt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmgt p0.b, p0/z, z0.b, z0.b fcmgt p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmgt p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmgt p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmgt p0.s, p0/z, z0.s, #1.0 fcmgt p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmgt p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmgt p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmgt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmgt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmla-diagnostics.s

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: fcmla z0.s, z1.s, z2.s[2], #0 // CHECK-NEXT: fcmla z0.s, z1.s, z2.s[2], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmla z0.d, z1.d, z2.d[0], #0 fcmla z0.d, z1.d, z2.d[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0 // CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p0/z, z28.s
fcmla z21.s, z10.s, z5.s[1], #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fcmla z21.s, z10.s, z5.s[1], #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmla.s

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f bf 64 <unknown> // CHECK-UNKNOWN: ff 1f bf 64 <unknown>
fcmla z21.s, z10.s, z5.s[1], #90 fcmla z21.s, z10.s, z5.s[1], #90
// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90
// CHECK-ENCODING: [0x55,0x15,0xf5,0x64] // CHECK-ENCODING: [0x55,0x15,0xf5,0x64]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 f5 64 <unknown> // CHECK-UNKNOWN: 55 15 f5 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
fcmla z4.d, p7/m, z31.d, z31.d, #270
// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 7f df 64 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
fcmla z4.d, p7/m, z31.d, z31.d, #270
// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 7f df 64 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
fcmla z21.s, z10.s, z5.s[1], #90
// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90
// CHECK-ENCODING: [0x55,0x15,0xf5,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 f5 64 <unknown>

test/MC/AArch64/SVE/fcmle-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmle p0.b, p0/z, z0.b, z0.b fcmle p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmle p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmle p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmle p0.s, p0/z, z0.s, #1.0 fcmle p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmle p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmle p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmle p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmle p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmlt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmlt p0.b, p0/z, z0.b, z0.b fcmlt p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmlt p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmlt p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmlt p0.s, p0/z, z0.s, #1.0 fcmlt p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmlt p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmlt p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmlt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmlt p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmne-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmne p0.b, p0/z, z0.b, z0.b fcmne p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmne p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmne p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmne p0.s, p0/z, z0.s, #1.0 fcmne p0.s, p0/z, z0.s, #1.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
// CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #1.0 // CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #1.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmne p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmne p0.d, p0/z, z0.d, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
fcmne p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmne p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcmuo-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcmuo p0.b, p0/z, z0.b, z0.b fcmuo p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: fcmuo p0.b, p0/z, z0.b, z0.b // CHECK-NEXT: fcmuo p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcmuo p0.s, p0/z, z0.s, #0.0 fcmuo p0.s, p0/z, z0.s, #0.0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
// CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, #0.0 // CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, #0.0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fcmuo p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcmuo p0.d, p0/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fcpy.s

Show First 20 Lines • Show All 1,548 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 c7 d0 05 <unknown> // CHECK-UNKNOWN: c0 c7 d0 05 <unknown>
fcpy z0.d, p0/m, #31.00000000 fcpy z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> // CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p0/z, z7.d
// CHECK-INST: movprfx z0.d, p0/z, z7.d
// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
fcpy z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fcpy z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>

test/MC/AArch64/SVE/fcvt.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 c9 65 <unknown> // CHECK-UNKNOWN: 00 a0 c9 65 <unknown>
fcvt z0.d, p0/m, z0.s fcvt z0.d, p0/m, z0.s
// CHECK-INST: fcvt z0.d, p0/m, z0.s // CHECK-INST: fcvt z0.d, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0xcb,0x65] // CHECK-ENCODING: [0x00,0xa0,0xcb,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 cb 65 <unknown> // CHECK-UNKNOWN: 00 a0 cb 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
fcvt z5.d, p0/m, z0.s
// CHECK-INST: fcvt z5.d, p0/m, z0.s
// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 cb 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
fcvt z5.d, p0/m, z0.s
// CHECK-INST: fcvt z5.d, p0/m, z0.s
// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 cb 65 <unknown>

test/MC/AArch64/SVE/fcvtzs.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 dc 65 <unknown> // CHECK-UNKNOWN: 00 a0 dc 65 <unknown>
fcvtzs z0.d, p0/m, z0.d fcvtzs z0.d, p0/m, z0.d
// CHECK-INST: fcvtzs z0.d, p0/m, z0.d // CHECK-INST: fcvtzs z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xde,0x65] // CHECK-ENCODING: [0x00,0xa0,0xde,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 de 65 <unknown> // CHECK-UNKNOWN: 00 a0 de 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
fcvtzs z5.d, p0/m, z0.d
// CHECK-INST: fcvtzs z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xde,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 de 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
fcvtzs z5.d, p0/m, z0.d
// CHECK-INST: fcvtzs z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xde,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 de 65 <unknown>

test/MC/AArch64/SVE/fcvtzu.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 dd 65 <unknown> // CHECK-UNKNOWN: 00 a0 dd 65 <unknown>
fcvtzu z0.d, p0/m, z0.d fcvtzu z0.d, p0/m, z0.d
// CHECK-INST: fcvtzu z0.d, p0/m, z0.d // CHECK-INST: fcvtzu z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xdf,0x65] // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 df 65 <unknown> // CHECK-UNKNOWN: 00 a0 df 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
fcvtzu z5.d, p0/m, z0.d
// CHECK-INST: fcvtzu z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 df 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
fcvtzu z5.d, p0/m, z0.d
// CHECK-INST: fcvtzu z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 df 65 <unknown>

test/MC/AArch64/SVE/fdiv.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 8d 65 <unknown> // CHECK-UNKNOWN: e0 9f 8d 65 <unknown>
fdiv z0.d, p7/m, z0.d, z31.d fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cd 65 <unknown> // CHECK-UNKNOWN: e0 9f cd 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cd 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cd 65 <unknown>

test/MC/AArch64/SVE/fdivr.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 8c 65 <unknown> // CHECK-UNKNOWN: e0 9f 8c 65 <unknown>
fdivr z0.d, p7/m, z0.d, z31.d fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cc 65 <unknown> // CHECK-UNKNOWN: e0 9f cc 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cc 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f cc 65 <unknown>

test/MC/AArch64/SVE/fdup-diagnostics.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant
// CHECK-NEXT: fdup z0.s, #64.00000000 // r = 5, n = 32 // CHECK-NEXT: fdup z0.s, #64.00000000 // r = 5, n = 32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fdup z0.d, #64.00000000 // r = 5, n = 32 fdup z0.d, #64.00000000 // r = 5, n = 32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant
// CHECK-NEXT: fdup z0.d, #64.00000000 // r = 5, n = 32 // CHECK-NEXT: fdup z0.d, #64.00000000 // r = 5, n = 32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fdup z0.d, #31.00000000
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fdup z0.d, #31.00000000
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fdup z0.d, #31.00000000
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fdup z0.d, #31.00000000
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fexpa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid destination or source register. // Invalid destination or source register.
fexpa z0.b, z31.b fexpa z0.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fexpa z0.b, z31.b // CHECK-NEXT: fexpa z0.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fexpa z0.s, z31.d fexpa z0.s, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fexpa z0.s, z31.d // CHECK-NEXT: fexpa z0.s, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fexpa z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fexpa z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fexpa z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fexpa z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmad.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 9c bf 65 <unknown> // CHECK-UNKNOWN: 20 9c bf 65 <unknown>
fmad z0.d, p7/m, z1.d, z31.d fmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] // CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 9c ff 65 <unknown> // CHECK-UNKNOWN: 20 9c ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 9c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 9c ff 65 <unknown>

test/MC/AArch64/SVE/fmax.s

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 86 65 <unknown> // CHECK-UNKNOWN: e0 9f 86 65 <unknown>
fmax z0.d, p7/m, z0.d, z31.d fmax z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c6 65 <unknown> // CHECK-UNKNOWN: e0 9f c6 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p0/z, z7.d
// CHECK-INST: movprfx z0.d, p0/z, z7.d
// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
fmax z0.d, p0/m, z0.d, #0.0
// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0
// CHECK-ENCODING: [0x00,0x80,0xde,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 de 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmax z0.d, p0/m, z0.d, #0.0
// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0
// CHECK-ENCODING: [0x00,0x80,0xde,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 de 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmax z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c6 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmax z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c6 65 <unknown>

test/MC/AArch64/SVE/fmaxnm.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 84 65 <unknown> // CHECK-UNKNOWN: e0 9f 84 65 <unknown>
fmaxnm z0.d, p7/m, z0.d, z31.d fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c4 65 <unknown> // CHECK-UNKNOWN: e0 9f c4 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fmaxnm z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c dc 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fmaxnm z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c dc 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c4 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c4 65 <unknown>

test/MC/AArch64/SVE/fmaxnmv-diagnostics.s

Show All 11 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fmaxnmv v0, p7, z31.h fmaxnmv v0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxnmv v0, p7, z31.h // CHECK-NEXT: fmaxnmv v0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
fmaxnmv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmaxnmv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fmaxnmv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmaxnmv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmaxv-diagnostics.s

Show All 11 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fmaxv v0, p7, z31.h fmaxv v0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxv v0, p7, z31.h // CHECK-NEXT: fmaxv v0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
fmaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fmaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmin.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 87 65 <unknown> // CHECK-UNKNOWN: e0 9f 87 65 <unknown>
fmin z0.d, p7/m, z0.d, z31.d fmin z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c7 65 <unknown> // CHECK-UNKNOWN: e0 9f c7 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fmin z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c df 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fmin z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c df 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmin z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c7 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmin z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c7 65 <unknown>

test/MC/AArch64/SVE/fminnm.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 85 65 <unknown> // CHECK-UNKNOWN: e0 9f 85 65 <unknown>
fminnm z0.d, p7/m, z0.d, z31.d fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c5 65 <unknown> // CHECK-UNKNOWN: e0 9f c5 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fminnm z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c dd 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fminnm z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c dd 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c5 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c5 65 <unknown>

test/MC/AArch64/SVE/fminnmv-diagnostics.s

Show All 11 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fminnmv v0, p7, z31.h fminnmv v0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminnmv v0, p7, z31.h // CHECK-NEXT: fminnmv v0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
fminnmv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fminnmv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fminnmv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fminnmv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fminv-diagnostics.s

Show All 11 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fminv v0, p7, z31.h fminv v0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminv v0, p7, z31.h // CHECK-NEXT: fminv v0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
fminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmla-diagnostics.s

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1] // CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmla z0.d, z1.d, z2.d[2] fmla z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: fmla z0.d, z1.d, z2.d[2] // CHECK-NEXT: fmla z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fmla z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmla z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmla.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 bf 64 <unknown> // CHECK-UNKNOWN: 20 00 bf 64 <unknown>
fmla z0.d, z1.d, z7.d[1] fmla z0.d, z1.d, z7.d[1]
// CHECK-INST: fmla z0.d, z1.d, z7.d[1] // CHECK-INST: fmla z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x00,0xf7,0x64] // CHECK-ENCODING: [0x20,0x00,0xf7,0x64]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 f7 64 <unknown> // CHECK-UNKNOWN: 20 00 f7 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmla z0.d, z1.d, z7.d[1]
// CHECK-INST: fmla z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x00,0xf7,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 f7 64 <unknown>

test/MC/AArch64/SVE/fmls-diagnostics.s

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: fmls z0.d, z1.d, z2.d[-1] // CHECK-NEXT: fmls z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmls z0.d, z1.d, z2.d[2] fmls z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: fmls z0.d, z1.d, z2.d[2] // CHECK-NEXT: fmls z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fmls z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmls z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmls.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 bf 64 <unknown> // CHECK-UNKNOWN: 20 04 bf 64 <unknown>
fmls z0.d, z1.d, z7.d[1] fmls z0.d, z1.d, z7.d[1]
// CHECK-INST: fmls z0.d, z1.d, z7.d[1] // CHECK-INST: fmls z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x04,0xf7,0x64] // CHECK-ENCODING: [0x20,0x04,0xf7,0x64]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 f7 64 <unknown> // CHECK-UNKNOWN: 20 04 f7 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmls z0.d, z1.d, z7.d[1]
// CHECK-INST: fmls z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x04,0xf7,0x64]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 f7 64 <unknown>

test/MC/AArch64/SVE/fmov-diagnostics.s

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant
// CHECK-NEXT: fmov z0.s, p0/m, #64.00000000 // r = 5, n = 32 // CHECK-NEXT: fmov z0.s, p0/m, #64.00000000 // r = 5, n = 32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant
// CHECK-NEXT: fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 // CHECK-NEXT: fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fmov z0.d, #31.00000000
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmov z0.d, #31.00000000
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fmov z0.d, #31.00000000
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmov z0.d, #31.00000000
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmov.s

Show First 20 Lines • Show All 1,590 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 c7 d0 05 <unknown> // CHECK-UNKNOWN: c0 c7 d0 05 <unknown>
fmov z0.d, p0/m, #31.00000000 fmov z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> // CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p0/z, z7.d
// CHECK-INST: movprfx z0.d, p0/z, z7.d
// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
fmov z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmov z0.d, p0/m, #31.00000000
// CHECK-INST: fmov z0.d, p0/m, #31.00000000
// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>

test/MC/AArch64/SVE/fmsb.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc bf 65 <unknown> // CHECK-UNKNOWN: 20 bc bf 65 <unknown>
fmsb z0.d, p7/m, z1.d, z31.d fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] // CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc ff 65 <unknown> // CHECK-UNKNOWN: 20 bc ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc ff 65 <unknown>

test/MC/AArch64/SVE/fmul-diagnostics.s

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmul z0.h, p8/m, z0.h, z31.h fmul z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fmul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fmul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
fmul z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
fmul z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmul.s

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 08 9f 65 <unknown> // CHECK-UNKNOWN: 20 08 9f 65 <unknown>
fmul z0.d, z1.d, z31.d fmul z0.d, z1.d, z31.d
// CHECK-INST: fmul z0.d, z1.d, z31.d // CHECK-INST: fmul z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x08,0xdf,0x65] // CHECK-ENCODING: [0x20,0x08,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 08 df 65 <unknown> // CHECK-UNKNOWN: 20 08 df 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fmul z31.d, p7/m, z31.d, #2.0
// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fmul z31.d, p7/m, z31.d, #2.0
// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmul z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmul z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c2 65 <unknown>

test/MC/AArch64/SVE/fmulx.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 8a 65 <unknown> // CHECK-UNKNOWN: e0 9f 8a 65 <unknown>
fmulx z0.d, p7/m, z0.d, z31.d fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f ca 65 <unknown> // CHECK-UNKNOWN: e0 9f ca 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f ca 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f ca 65 <unknown>

test/MC/AArch64/SVE/fneg.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 9d 04 <unknown> // CHECK-UNKNOWN: ff bf 9d 04 <unknown>
fneg z31.d, p7/m, z31.d fneg z31.d, p7/m, z31.d
// CHECK-INST: fneg z31.d, p7/m, z31.d // CHECK-INST: fneg z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xdd,0x04] // CHECK-ENCODING: [0xff,0xbf,0xdd,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf dd 04 <unknown> // CHECK-UNKNOWN: ff bf dd 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
fneg z4.d, p7/m, z31.d
// CHECK-INST: fneg z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf dd 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
fneg z4.d, p7/m, z31.d
// CHECK-INST: fneg z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf dd 04 <unknown>

test/MC/AArch64/SVE/fnmad.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 dc bf 65 <unknown> // CHECK-UNKNOWN: 20 dc bf 65 <unknown>
fnmad z0.d, p7/m, z1.d, z31.d fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] // CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 dc ff 65 <unknown> // CHECK-UNKNOWN: 20 dc ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 dc ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 dc ff 65 <unknown>

test/MC/AArch64/SVE/fnmla.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c bf 65 <unknown> // CHECK-UNKNOWN: 20 5c bf 65 <unknown>
fnmla z0.d, p7/m, z1.d, z31.d fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] // CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c ff 65 <unknown> // CHECK-UNKNOWN: 20 5c ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c ff 65 <unknown>

test/MC/AArch64/SVE/fnmls.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c bf 65 <unknown> // CHECK-UNKNOWN: 20 7c bf 65 <unknown>
fnmls z0.d, p7/m, z1.d, z31.d fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] // CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c ff 65 <unknown> // CHECK-UNKNOWN: 20 7c ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c ff 65 <unknown>

test/MC/AArch64/SVE/fnmsb.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fc bf 65 <unknown> // CHECK-UNKNOWN: 20 fc bf 65 <unknown>
fnmsb z0.d, p7/m, z1.d, z31.d fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] // CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fc ff 65 <unknown> // CHECK-UNKNOWN: 20 fc ff 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fc ff 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fc ff 65 <unknown>

test/MC/AArch64/SVE/frecpe-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frecpe z0.b, z31.b frecpe z0.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frecpe z0.b, z31.b // CHECK-NEXT: frecpe z0.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
frecpe z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frecpe z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
frecpe z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frecpe z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/frecps-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
frecps z0.b, z1.b, z2.b frecps z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frecps z0.b, z1.b, z2.b // CHECK-NEXT: frecps z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frecps z0.h, z1.s, z2.s frecps z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frecps z0.h, z1.s, z2.s // CHECK-NEXT: frecps z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
frecps z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frecps z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
frecps z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frecps z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/frecpx.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 8c 65 <unknown> // CHECK-UNKNOWN: ff bf 8c 65 <unknown>
frecpx z31.d, p7/m, z31.d frecpx z31.d, p7/m, z31.d
// CHECK-INST: frecpx z31.d, p7/m, z31.d // CHECK-INST: frecpx z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xcc,0x65] // CHECK-ENCODING: [0xff,0xbf,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf cc 65 <unknown> // CHECK-UNKNOWN: ff bf cc 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frecpx z4.d, p7/m, z31.d
// CHECK-INST: frecpx z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf cc 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frecpx z4.d, p7/m, z31.d
// CHECK-INST: frecpx z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf cc 65 <unknown>

test/MC/AArch64/SVE/frinta.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 84 65 <unknown> // CHECK-UNKNOWN: ff bf 84 65 <unknown>
frinta z31.d, p7/m, z31.d frinta z31.d, p7/m, z31.d
// CHECK-INST: frinta z31.d, p7/m, z31.d // CHECK-INST: frinta z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc4,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c4 65 <unknown> // CHECK-UNKNOWN: ff bf c4 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frinta z4.d, p7/m, z31.d
// CHECK-INST: frinta z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c4 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frinta z4.d, p7/m, z31.d
// CHECK-INST: frinta z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c4 65 <unknown>

test/MC/AArch64/SVE/frinti.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 87 65 <unknown> // CHECK-UNKNOWN: ff bf 87 65 <unknown>
frinti z31.d, p7/m, z31.d frinti z31.d, p7/m, z31.d
// CHECK-INST: frinti z31.d, p7/m, z31.d // CHECK-INST: frinti z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc7,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c7 65 <unknown> // CHECK-UNKNOWN: ff bf c7 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frinti z4.d, p7/m, z31.d
// CHECK-INST: frinti z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c7 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frinti z4.d, p7/m, z31.d
// CHECK-INST: frinti z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c7 65 <unknown>

test/MC/AArch64/SVE/frintm.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 82 65 <unknown> // CHECK-UNKNOWN: ff bf 82 65 <unknown>
frintm z31.d, p7/m, z31.d frintm z31.d, p7/m, z31.d
// CHECK-INST: frintm z31.d, p7/m, z31.d // CHECK-INST: frintm z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc2,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c2 65 <unknown> // CHECK-UNKNOWN: ff bf c2 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frintm z4.d, p7/m, z31.d
// CHECK-INST: frintm z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c2 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frintm z4.d, p7/m, z31.d
// CHECK-INST: frintm z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c2 65 <unknown>

test/MC/AArch64/SVE/frintn.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 80 65 <unknown> // CHECK-UNKNOWN: ff bf 80 65 <unknown>
frintn z31.d, p7/m, z31.d frintn z31.d, p7/m, z31.d
// CHECK-INST: frintn z31.d, p7/m, z31.d // CHECK-INST: frintn z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc0,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c0 65 <unknown> // CHECK-UNKNOWN: ff bf c0 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frintn z4.d, p7/m, z31.d
// CHECK-INST: frintn z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c0 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frintn z4.d, p7/m, z31.d
// CHECK-INST: frintn z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c0 65 <unknown>

test/MC/AArch64/SVE/frintp.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 81 65 <unknown> // CHECK-UNKNOWN: ff bf 81 65 <unknown>
frintp z31.d, p7/m, z31.d frintp z31.d, p7/m, z31.d
// CHECK-INST: frintp z31.d, p7/m, z31.d // CHECK-INST: frintp z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc1,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c1 65 <unknown> // CHECK-UNKNOWN: ff bf c1 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frintp z4.d, p7/m, z31.d
// CHECK-INST: frintp z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c1 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frintp z4.d, p7/m, z31.d
// CHECK-INST: frintp z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c1 65 <unknown>

test/MC/AArch64/SVE/frintx.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 86 65 <unknown> // CHECK-UNKNOWN: ff bf 86 65 <unknown>
frintx z31.d, p7/m, z31.d frintx z31.d, p7/m, z31.d
// CHECK-INST: frintx z31.d, p7/m, z31.d // CHECK-INST: frintx z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc6,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c6 65 <unknown> // CHECK-UNKNOWN: ff bf c6 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frintx z4.d, p7/m, z31.d
// CHECK-INST: frintx z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c6 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frintx z4.d, p7/m, z31.d
// CHECK-INST: frintx z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c6 65 <unknown>

test/MC/AArch64/SVE/frintz.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 83 65 <unknown> // CHECK-UNKNOWN: ff bf 83 65 <unknown>
frintz z31.d, p7/m, z31.d frintz z31.d, p7/m, z31.d
// CHECK-INST: frintz z31.d, p7/m, z31.d // CHECK-INST: frintz z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc3,0x65] // CHECK-ENCODING: [0xff,0xbf,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf c3 65 <unknown> // CHECK-UNKNOWN: ff bf c3 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
frintz z4.d, p7/m, z31.d
// CHECK-INST: frintz z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c3 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
frintz z4.d, p7/m, z31.d
// CHECK-INST: frintz z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf c3 65 <unknown>

test/MC/AArch64/SVE/frsqrte-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frsqrte z0.b, z31.b frsqrte z0.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frsqrte z0.b, z31.b // CHECK-NEXT: frsqrte z0.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
frsqrte z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frsqrte z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
frsqrte z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frsqrte z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/frsqrts-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
frsqrts z0.b, z1.b, z2.b frsqrts z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frsqrts z0.b, z1.b, z2.b // CHECK-NEXT: frsqrts z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frsqrts z0.h, z1.s, z2.s frsqrts z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frsqrts z0.h, z1.s, z2.s // CHECK-NEXT: frsqrts z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
frsqrts z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
frsqrts z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fscale.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 89 65 <unknown> // CHECK-UNKNOWN: e0 9f 89 65 <unknown>
fscale z0.d, p7/m, z0.d, z31.d fscale z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d // CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c9 65 <unknown> // CHECK-UNKNOWN: e0 9f c9 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fscale z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c9 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fscale z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c9 65 <unknown>

test/MC/AArch64/SVE/fsqrt.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 8d 65 <unknown> // CHECK-UNKNOWN: ff bf 8d 65 <unknown>
fsqrt z31.d, p7/m, z31.d fsqrt z31.d, p7/m, z31.d
// CHECK-INST: fsqrt z31.d, p7/m, z31.d // CHECK-INST: fsqrt z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xcd,0x65] // CHECK-ENCODING: [0xff,0xbf,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf cd 65 <unknown> // CHECK-UNKNOWN: ff bf cd 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
fsqrt z4.d, p7/m, z31.d
// CHECK-INST: fsqrt z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf cd 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
fsqrt z4.d, p7/m, z31.d
// CHECK-INST: fsqrt z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf cd 65 <unknown>

test/MC/AArch64/SVE/fsub-diagnostics.s

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fsub z0.h, p8/m, z0.h, z31.h fsub z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
fsub z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fsub z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fsub z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fsub z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fsub.s

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 9f 65 <unknown> // CHECK-UNKNOWN: 20 04 9f 65 <unknown>
fsub z0.d, z1.d, z31.d fsub z0.d, z1.d, z31.d
// CHECK-INST: fsub z0.d, z1.d, z31.d // CHECK-INST: fsub z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x04,0xdf,0x65] // CHECK-ENCODING: [0x20,0x04,0xdf,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 df 65 <unknown> // CHECK-UNKNOWN: 20 04 df 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fsub z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c d9 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fsub z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c d9 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fsub z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c1 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fsub z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c1 65 <unknown>

test/MC/AArch64/SVE/fsubr.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f 83 65 <unknown> // CHECK-UNKNOWN: e0 9f 83 65 <unknown>
fsubr z0.d, p7/m, z0.d, z31.d fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c3 65 <unknown> // CHECK-UNKNOWN: e0 9f c3 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
fsubr z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fsubr z31.d, p7/m, z31.d, #1.0
// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0
// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c3 65 <unknown>

test/MC/AArch64/SVE/ftmad-diagnostics.s

Show All 30 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #-1 // CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ftmad z0.h, z0.h, z1.h, #8 ftmad z0.h, z0.h, z1.h, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #8 // CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ftmad z0.d, z0.d, z31.d, #7
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: ftmad z0.d, z0.d, z31.d, #7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ftmad.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 83 97 65 <unknown> // CHECK-UNKNOWN: e0 83 97 65 <unknown>
ftmad z0.d, z0.d, z31.d, #7 ftmad z0.d, z0.d, z31.d, #7
// CHECK-INST: ftmad z0.d, z0.d, z31.d, #7 // CHECK-INST: ftmad z0.d, z0.d, z31.d, #7
// CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] // CHECK-ENCODING: [0xe0,0x83,0xd7,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 83 d7 65 <unknown> // CHECK-UNKNOWN: e0 83 d7 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
ftmad z0.d, z0.d, z31.d, #7
// CHECK-INST: ftmad z0.d, z0.d, z31.d, #7
// CHECK-ENCODING: [0xe0,0x83,0xd7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 83 d7 65 <unknown>

test/MC/AArch64/SVE/ftsmul-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
ftsmul z0.b, z1.b, z2.b ftsmul z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ftsmul z0.b, z1.b, z2.b // CHECK-NEXT: ftsmul z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ftsmul z0.h, z1.s, z2.s ftsmul z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ftsmul z0.h, z1.s, z2.s // CHECK-NEXT: ftsmul z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ftsmul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ftsmul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ftssel-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
ftssel z0.b, z1.b, z31.b ftssel z0.b, z1.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ftssel z0.b, z1.b, z31.b // CHECK-NEXT: ftssel z0.b, z1.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ftssel z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ftssel z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ftssel z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ftssel z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/incd-diagnostics.s

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: incd x0, #-1 // CHECK-NEXT: incd x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incd x0, #32 incd x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: incd x0, #32 // CHECK-NEXT: incd x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
incd z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incd z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
incd z0.d, all, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incd z0.d, all, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
incd z0.d, all
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incd z0.d, all
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/incd.s

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 e1 f0 04 <unknown> // CHECK-UNKNOWN: c0 e1 f0 04 <unknown>
incd x0, #28 incd x0, #28
// CHECK-INST: incd x0, #28 // CHECK-INST: incd x0, #28
// CHECK-ENCODING: [0x80,0xe3,0xf0,0x04] // CHECK-ENCODING: [0x80,0xe3,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e3 f0 04 <unknown> // CHECK-UNKNOWN: 80 e3 f0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incd z0.d
// CHECK-INST: incd z0.d
// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incd z0.d, all, mul #16
// CHECK-INST: incd z0.d, all, mul #16
// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incd z0.d, all
// CHECK-INST: incd z0.d
// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>

test/MC/AArch64/SVE/inch-diagnostics.s

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: inch x0, #-1 // CHECK-NEXT: inch x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
inch x0, #32 inch x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: inch x0, #32 // CHECK-NEXT: inch x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
inch z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: inch z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
inch z0.h, all, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: inch z0.h, all, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
inch z0.h, all
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: inch z0.h, all
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/inch.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 e1 70 04 <unknown> // CHECK-UNKNOWN: c0 e1 70 04 <unknown>
inch x0, #28 inch x0, #28
// CHECK-INST: inch x0, #28 // CHECK-INST: inch x0, #28
// CHECK-ENCODING: [0x80,0xe3,0x70,0x04] // CHECK-ENCODING: [0x80,0xe3,0x70,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e3 70 04 <unknown> // CHECK-UNKNOWN: 80 e3 70 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
inch z0.h
// CHECK-INST: inch z0.h
// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
inch z0.h, all, mul #16
// CHECK-INST: inch z0.h, all, mul #16
// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
inch z0.h, all
// CHECK-INST: inch z0.h
// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 70 04 <unknown>

test/MC/AArch64/SVE/incp-diagnostics.s

Show All 30 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: incp x0, p0/m // CHECK-NEXT: incp x0, p0/m
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incp x0, p0.q incp x0, p0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: incp x0, p0.q // CHECK-NEXT: incp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
incp z31.d, p7
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incp z31.d, p7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/incp.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown> // CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.d, p15 incp z31.d, p15
// CHECK-INST: incp z31.d, p15 // CHECK-INST: incp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xec,0x25] // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown> // CHECK-UNKNOWN: ff 81 ec 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
incp z31.d, p15
// CHECK-INST: incp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>

test/MC/AArch64/SVE/incw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: incw x0, #-1 // CHECK-NEXT: incw x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incw x0, #32 incw x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: incw x0, #32 // CHECK-NEXT: incw x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
incw z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incw z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
incw z0.s, all, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incw z0.s, all, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
incw z0.s, all
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: incw z0.s, all
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/incw.s

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 e1 b0 04 <unknown> // CHECK-UNKNOWN: c0 e1 b0 04 <unknown>
incw x0, #28 incw x0, #28
// CHECK-INST: incw x0, #28 // CHECK-INST: incw x0, #28
// CHECK-ENCODING: [0x80,0xe3,0xb0,0x04] // CHECK-ENCODING: [0x80,0xe3,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e3 b0 04 <unknown> // CHECK-UNKNOWN: 80 e3 b0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incw z0.s
// CHECK-INST: incw z0.s
// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incw z0.s, all, mul #16
// CHECK-INST: incw z0.s, all, mul #16
// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
incw z0.s, all
// CHECK-INST: incw z0.s
// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>

test/MC/AArch64/SVE/index-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: index z17.s, x9, w7 // CHECK-NEXT: index z17.s, x9, w7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
index z17.d, w9, w7 index z17.d, w9, w7
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
// CHECK-NEXT: index z17.d, w9, w7 // CHECK-NEXT: index z17.d, w9, w7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p0/z, z28.d
index z21.d, x10, x21
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z21.d, x10, x21
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
index z21.d, x10, x21
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z21.d, x10, x21
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.d, p0/z, z30.d
index z23.d, x13, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z23.d, x13, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
index z23.d, x13, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z23.d, x13, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.d, p0/z, z30.d
index z23.d, #13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z23.d, #13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
index z23.d, #13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: index z23.d, #13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/insr-diagnostics.s

Show All 37 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: insr z31.s, d0 // CHECK-NEXT: insr z31.s, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
insr z31.d, b0 insr z31.d, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: insr z31.d, b0 // CHECK-NEXT: insr z31.d, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
insr z31.d, xzr
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: insr z31.d, xzr
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z4.d, p0/z, z6.d
insr z4.d, d31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: insr z4.d, d31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/insr.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 3b b4 05 <unknown> // CHECK-UNKNOWN: ff 3b b4 05 <unknown>
insr z31.d, d31 insr z31.d, d31
// CHECK-INST: insr z31.d, d31 // CHECK-INST: insr z31.d, d31
// CHECK-ENCODING: [0xff,0x3b,0xf4,0x05] // CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 3b f4 05 <unknown> // CHECK-UNKNOWN: ff 3b f4 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
insr z31.d, xzr
// CHECK-INST: insr z31.d, xzr
// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
insr z4.d, d31
// CHECK-INST: insr z4.d, d31
// CHECK-ENCODING: [0xe4,0x3b,0xf4,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 3b f4 05 <unknown>

test/MC/AArch64/SVE/lasta-diagnostics.s

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lasta s0, p7, z31.d // CHECK-NEXT: lasta s0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
lasta d0, p7, z31.b lasta d0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lasta d0, p7, z31.b // CHECK-NEXT: lasta d0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
lasta x0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lasta x0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lasta x0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lasta x0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p7/z, z6.d
lasta d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lasta d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lasta d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lasta d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/lastb-diagnostics.s

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lastb s0, p7, z31.d // CHECK-NEXT: lastb s0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
lastb d0, p7, z31.b lastb d0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lastb d0, p7, z31.b // CHECK-NEXT: lastb d0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
lastb x0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lastb x0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lastb x0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lastb x0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p7/z, z6.d
lastb d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lastb d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lastb d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lastb d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1b-diagnostics.s

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #-1] // CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z0.d, p0/z, [z0.d, #32] ld1b z0.d, p0/z, [z0.d, #32]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32] // CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1b { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1b { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1d-diagnostics.s

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #256] // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #256]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d z0.d, p0/z, [z0.d, #3] ld1d z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1d { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1d { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1h-diagnostics.s

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #64] // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z0.d, p0/z, [z0.d, #3] ld1h z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1h { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1h { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rb-diagnostics.s

Show All 15 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rb z0.b, p8/z, [x0] ld1rb z0.b, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rb z0.b, p8/z, [x0] // CHECK-NEXT: ld1rb z0.b, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rb { z31.d }, p7/z, [sp, #63]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rb { z31.d }, p7/z, [sp, #63]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rd-diagnostics.s

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rd z0.d, p8/z, [x0] ld1rd z0.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rd z0.d, p8/z, [x0] // CHECK-NEXT: ld1rd z0.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rd { z31.d }, p7/z, [sp, #504]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rd { z31.d }, p7/z, [sp, #504]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rh-diagnostics.s

Show All 39 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rh z0.h, p8/z, [x0] ld1rh z0.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rh z0.h, p8/z, [x0] // CHECK-NEXT: ld1rh z0.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rh { z31.d }, p7/z, [sp, #126]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rh { z31.d }, p7/z, [sp, #126]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rqb-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1] // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1rqb z0.b, p0/z, [x0, w1, uxtw] ld1rqb z0.b, p0/z, [x0, w1, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1, uxtw] // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
ld1rqb { z21.b }, p5/z, [x10, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld1rqb { z21.b }, p5/z, [x10, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rqd-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, lsl #3] // CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] ld1rqd z0.d, p0/z, [x0, w1, uxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] // CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, uxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z23.d, p3/z, z30.d
ld1rqd { z23.d }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
ld1rqd { z23.d }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rqh-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, lsl #1] // CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] ld1rqh z0.h, p0/z, [x0, w1, uxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] // CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, uxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z23.h, p3/z, z30.h
ld1rqh { z23.h }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
ld1rqh { z23.h }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rqw-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, lsl #2] // CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] // CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z23.s, p3/z, z30.s
ld1rqw { z23.s }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
ld1rqw { z23.s }, p3/z, [x13, #112]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsb-diagnostics.s

Show All 24 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsb z0.h, p8/z, [x0] ld1rsb z0.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rsb z0.h, p8/z, [x0] // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rsb { z31.d }, p7/z, [sp, #63]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rsb { z31.d }, p7/z, [sp, #63]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsh-diagnostics.s

Show All 34 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsh z0.s, p8/z, [x0] ld1rsh z0.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rsh z0.s, p8/z, [x0] // CHECK-NEXT: ld1rsh z0.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rsh { z31.d }, p7/z, [sp, #126]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rsh { z31.d }, p7/z, [sp, #126]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsw-diagnostics.s

Show All 39 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsw z0.d, p8/z, [x0] ld1rsw z0.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rsw z0.d, p8/z, [x0] // CHECK-NEXT: ld1rsw z0.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rsw { z31.d }, p7/z, [sp, #252]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rsw { z31.d }, p7/z, [sp, #252]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rw-diagnostics.s

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rw z0.s, p8/z, [x0] ld1rw z0.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ld1rw z0.s, p8/z, [x0] // CHECK-NEXT: ld1rw z0.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
ld1rw { z31.d }, p7/z, [sp, #252]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ld1rw { z31.d }, p7/z, [sp, #252]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sb-diagnostics.s

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #-1] // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z0.d, p0/z, [z0.d, #32] ld1sb z0.d, p0/z, [z0.d, #32]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32] // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1sb { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1sb { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sh-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #64] // CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z0.d, p0/z, [z0.d, #3] ld1sh z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1sh { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1sh { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128] // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sw z0.d, p0/z, [z0.d, #3] ld1sw z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1sw { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1sw { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #128] // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #128]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z0.d, p0/z, [z0.d, #3] ld1w z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ld1w { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ld1w { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld2b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld2b { z0.b, z2.b }, p0/z, [x0] // CHECK-NEXT: ld2b { z0.b, z2.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2b { v0.2d, v1.2d }, p0/z, [x0] ld2b { v0.2d, v1.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2b { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NEXT: ld2b { v0.2d, v1.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld2d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld2d { z0.d, z2.d }, p0/z, [x0] // CHECK-NEXT: ld2d { z0.d, z2.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2d { v0.2d, v1.2d }, p0/z, [x0] ld2d { v0.2d, v1.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2d { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NEXT: ld2d { v0.2d, v1.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld2h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0] // CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { v0.2d, v1.2d }, p0/z, [x0] ld2h { v0.2d, v1.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld2w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld2w { z0.s, z2.s }, p0/z, [x0] // CHECK-NEXT: ld2w { z0.s, z2.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2w { v0.2d, v1.2d }, p0/z, [x0] ld2w { v0.2d, v1.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2w { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NEXT: ld2w { v0.2d, v1.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld3b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0] // CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld3d-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0] // CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld3h-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0] // CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld3w-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0] // CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld4b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0] // CHECK-NEXT: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NEXT: ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld4d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0] // CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld4h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0] // CHECK-NEXT: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NEXT: ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld4w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0] // CHECK-NEXT: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NEXT: ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1] // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1b z0.d, p0/z, [z0.d, #32] ldff1b z0.d, p0/z, [z0.d, #32]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32] // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1b { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1b { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #256] // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #256]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1d z0.d, p0/z, [z0.d, #3] ldff1d z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1d { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1d { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #64] // CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1h z0.d, p0/z, [z0.d, #3] ldff1h z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1h { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1h { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1sb-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #-1] // CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sb z0.d, p0/z, [z0.d, #32] ldff1sb z0.d, p0/z, [z0.d, #32]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32] // CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1sb { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1sb { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1sh-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #64] // CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sh z0.d, p0/z, [z0.d, #3] ldff1sh z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1sh { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1sh { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1sw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #128] // CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #128]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sw z0.d, p0/z, [z0.d, #3] ldff1sw z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1sw { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1sw { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldff1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #128] // CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #128]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1w z0.d, p0/z, [z0.d, #3] ldff1w z0.d, p0/z, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3] // CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldff1w { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldff1w { z0.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1sb-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1sh-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1sw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnf1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnt1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
ldnt1b { z0.b }, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1b { z0.b }, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnt1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnt1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ldnt1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/lsl-diagnostics.s

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// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
lsl z0.b, p8/m, z0.b, z1.b lsl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
lsl z31.d, z31.d, #63
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsl z31.d, z31.d, #63
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lsl z31.d, z31.d, #63
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsl z31.d, z31.d, #63
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
lsl z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsl z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
lsl z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsl z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/lsl.s

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 8c 62 04 <unknown> // CHECK-UNKNOWN: 20 8c 62 04 <unknown>
lsl z0.s, z1.s, z2.d lsl z0.s, z1.s, z2.d
// CHECK-INST: lsl z0.s, z1.s, z2.d // CHECK-INST: lsl z0.s, z1.s, z2.d
// CHECK-ENCODING: [0x20,0x8c,0xa2,0x04] // CHECK-ENCODING: [0x20,0x8c,0xa2,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 8c a2 04 <unknown> // CHECK-UNKNOWN: 20 8c a2 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
lsl z31.d, p0/m, z31.d, #63
// CHECK-INST: lsl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 83 c3 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
lsl z31.d, p0/m, z31.d, #63
// CHECK-INST: lsl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 83 c3 04 <unknown>
movprfx z0.s, p0/z, z7.s
// CHECK-INST: movprfx z0.s, p0/z, z7.s
// CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 90 04 <unknown>
lsl z0.s, p0/m, z0.s, z1.d
// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x9b,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 9b 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
lsl z0.s, p0/m, z0.s, z1.d
// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x9b,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 9b 04 <unknown>

test/MC/AArch64/SVE/lslr.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 97 04 <unknown> // CHECK-UNKNOWN: 00 80 97 04 <unknown>
lslr z0.d, p0/m, z0.d, z0.d lslr z0.d, p0/m, z0.d, z0.d
// CHECK-INST: lslr z0.d, p0/m, z0.d, z0.d // CHECK-INST: lslr z0.d, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x80,0xd7,0x04] // CHECK-ENCODING: [0x00,0x80,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 d7 04 <unknown> // CHECK-UNKNOWN: 00 80 d7 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
lslr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d7 04 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
lslr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d7 04 <unknown>

test/MC/AArch64/SVE/lsr-diagnostics.s

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
lsr z0.b, p8/m, z0.b, z1.b lsr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
lsr z31.d, z31.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsr z31.d, z31.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
lsr z31.d, z31.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsr z31.d, z31.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
lsr z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsr z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
lsr z0.s, z1.s, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: lsr z0.s, z1.s, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/lsr.s

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 84 62 04 <unknown> // CHECK-UNKNOWN: 20 84 62 04 <unknown>
lsr z0.s, z1.s, z2.d lsr z0.s, z1.s, z2.d
// CHECK-INST: lsr z0.s, z1.s, z2.d // CHECK-INST: lsr z0.s, z1.s, z2.d
// CHECK-ENCODING: [0x20,0x84,0xa2,0x04] // CHECK-ENCODING: [0x20,0x84,0xa2,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 84 a2 04 <unknown> // CHECK-UNKNOWN: 20 84 a2 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
lsr z31.d, p0/m, z31.d, #64
// CHECK-INST: lsr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 81 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
lsr z31.d, p0/m, z31.d, #64
// CHECK-INST: lsr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 80 81 04 <unknown>
movprfx z0.s, p0/z, z7.s
// CHECK-INST: movprfx z0.s, p0/z, z7.s
// CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 20 90 04 <unknown>
lsr z0.s, p0/m, z0.s, z1.d
// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x99,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 99 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
lsr z0.s, p0/m, z0.s, z1.d
// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d
// CHECK-ENCODING: [0x20,0x80,0x99,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 80 99 04 <unknown>

test/MC/AArch64/SVE/lsrr.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 95 04 <unknown> // CHECK-UNKNOWN: 00 80 95 04 <unknown>
lsrr z0.d, p0/m, z0.d, z0.d lsrr z0.d, p0/m, z0.d, z0.d
// CHECK-INST: lsrr z0.d, p0/m, z0.d, z0.d // CHECK-INST: lsrr z0.d, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x80,0xd5,0x04] // CHECK-ENCODING: [0x00,0x80,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 d5 04 <unknown> // CHECK-UNKNOWN: 00 80 d5 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
lsrr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d5 04 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
lsrr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x80,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 80 d5 04 <unknown>

test/MC/AArch64/SVE/mad.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 df 81 04 <unknown> // CHECK-UNKNOWN: e0 df 81 04 <unknown>
mad z0.d, p7/m, z1.d, z31.d mad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d // CHECK-INST: mad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 df c1 04 <unknown> // CHECK-UNKNOWN: e0 df c1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
mad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 df c1 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mad z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 df c1 04 <unknown>

test/MC/AArch64/SVE/mla.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c 9f 04 <unknown> // CHECK-UNKNOWN: 20 5c 9f 04 <unknown>
mla z0.d, p7/m, z1.d, z31.d mla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d // CHECK-INST: mla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c df 04 <unknown> // CHECK-UNKNOWN: 20 5c df 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
mla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c df 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mla z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 5c df 04 <unknown>

test/MC/AArch64/SVE/mls.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c 9f 04 <unknown> // CHECK-UNKNOWN: 20 7c 9f 04 <unknown>
mls z0.d, p7/m, z1.d, z31.d mls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d // CHECK-INST: mls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c df 04 <unknown> // CHECK-UNKNOWN: 20 7c df 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
mls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c df 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mls z0.d, p7/m, z1.d, z31.d
// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 7c df 04 <unknown>

test/MC/AArch64/SVE/mov-diagnostics.s

Show First 20 Lines • Show All 406 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mov z22.q, z7.q[-1] // CHECK-NEXT: mov z22.q, z7.q[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z24.q, z21.q[4] mov z24.q, z21.q[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mov z24.q, z21.q[4] // CHECK-NEXT: mov z24.q, z21.q[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b
mov z31.b, wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.b, wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
mov z31.b, wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.b, wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
mov z0.d, #0xe0000000000003ff
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z0.d, #0xe0000000000003ff
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
mov z0.d, #0xe0000000000003ff
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z0.d, #0xe0000000000003ff
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z4.d, p7/z, z6.d
mov z4.d, p7/m, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z4.d, p7/m, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
mov z31.d, p15/m, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.d, p15/m, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
mov z0.d, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z0.d, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
mov z0.d, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z0.d, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
mov z31.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
mov z31.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
mov z31.d, z31.d[7]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.d, z31.d[7]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
mov z31.d, z31.d[7]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mov z31.d, z31.d[7]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/mov.s

Show First 20 Lines • Show All 654 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 00 25 <unknown> // CHECK-UNKNOWN: 00 40 00 25 <unknown>
mov p15.b, p15/z, p15.b mov p15.b, p15/z, p15.b
// CHECK-INST: mov p15.b, p15/z, p15.b // CHECK-INST: mov p15.b, p15/z, p15.b
// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 7d 0f 25 <unknown> // CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p7/z, z6.d
// CHECK-INST: movprfx z31.d, p7/z, z6.d
// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 3c d0 04 <unknown>
mov z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
mov z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
movprfx z21.d, p7/z, z28.d
// CHECK-INST: movprfx z21.d, p7/z, z28.d
// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 3f d0 04 <unknown>
mov z21.d, p7/m, #-128, lsl #8
// CHECK-INST: mov z21.d, p7/m, #-32768
// CHECK-ENCODING: [0x15,0x70,0xd7,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 70 d7 05 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
mov z21.d, p15/m, #-128, lsl #8
// CHECK-INST: mov z21.d, p15/m, #-32768
// CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 70 df 05 <unknown>
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
mov z4.d, p7/m, d31
// CHECK-INST: mov z4.d, p7/m, d31
// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
mov z4.d, p7/m, d31
// CHECK-INST: mov z4.d, p7/m, d31
// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f e0 05 <unknown>

test/MC/AArch64/SVE/movprfx-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
// ------------------------------------------------------------------------- //
// Different destination register (unary)
movprfx z0, z1
abs z2.d, p0/m, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination
// CHECK-NEXT: abs z2.d, p0/m, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different destination register (binary)
movprfx z0, z1
add z2.d, p0/m, z2.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination
// CHECK-NEXT: add z2.d, p0/m, z2.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different destination register (wide element)
movprfx z0, z1
asr z2.s, p0/m, z2.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination
// CHECK-NEXT: asr z2.s, p0/m, z2.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different destination register (ternary)
movprfx z0, z1
mla z3.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination
// CHECK-NEXT: mla z3.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Destination used in other operand (unary)
movprfx z0, z1
abs z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: abs z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z1.d
cpy z0.d, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: cpy z0.d, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z1.d
mov z0.d, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: mov z0.d, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Destination used in other operand (binary)
movprfx z0, z1
add z0.d, p0/m, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: add z0.d, p0/m, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Destination used in other operand (wide element)
movprfx z0, z1
asr z0.s, p0/m, z0.s, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: asr z0.s, p0/m, z0.s, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Destination used in other operand (ternary)
movprfx z0, z1
mla z0.d, p0/m, z0.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: mla z0.d, p0/m, z0.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different general predicate (unary)
movprfx z0.d, p0/m, z1.d
abs z0.d, p1/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate
// CHECK-NEXT: abs z0.d, p1/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different general predicate (binary)
movprfx z0.d, p0/m, z1.d
add z0.d, p1/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate
// CHECK-NEXT: add z0.d, p1/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different general predicate (wide element)
movprfx z0.d, p0/m, z1.d
asr z0.s, p1/m, z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate
// CHECK-NEXT: asr z0.s, p1/m, z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different general predicate (ternary)
movprfx z0.d, p0/m, z1.d
mla z0.d, p1/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate
// CHECK-NEXT: mla z0.d, p1/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different element size (unary)
movprfx z0.s, p0/m, z1.s
abs z0.d, p0/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: abs z0.d, p0/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different element size (binary)
movprfx z0.s, p0/m, z1.s
add z0.d, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different element size (wide element)
movprfx z0.d, p0/m, z1.d
asr z0.s, p0/m, z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different element size (ternary)
movprfx z0.s, p0/m, z1.s
mla z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Predicated movprfx with non-predicated instruction.
movprfx z0.d, p0/m, z1.d
add z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: add z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Ensure we don't try to apply a prefix to subsequent instructions (upon failure)
movprfx z0, z1
add z0.d, z1.d, z2.d
add z0.d, z1.d, z2.d
// CHECK: [[@LINE-2]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: add z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
// CHECK: add z0.d, z1.d, z2.d

test/MC/AArch64/SVE/movprfx.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// This test file is mostly empty because most 'movprfx' tests are embedded
// with other instructions that are destructive and can be prefixed
// by the movprfx instruction. A list of destructive instructions
// is given below by their mnemonic, which have tests in corresponding
// <mnemonic>.s test files:
//
// abs decp fdivr fnmla fsubr mov sdivr sqincw umulh
// add eon fmad fnmls ftmad msb sdot sqsub uqadd
// and eor fmax fnmsb incd mul smax sub uqdecd
// asr ext fmaxnm frecpx inch neg smin subr uqdech
// asrd fabd fmin frinta incp not smulh sxtb uqdecp
// asrr fabs fminnm frinti incw orn splice sxth uqdecw
// bic fadd fmla frintm insr orr sqadd sxtw uqincd
// clasta fcadd fmls frintn lsl rbit sqdecd uabd uqinch
// clastb fcmla fmov frintp lslr revb sqdech ucvtf uqincp
// cls fcpy fmsb frintx lsr revh sqdecp udiv uqincw
// clz fcvt fmul frintz lsrr revw sqdecw udivr uqsub
// cnot fcvtzs fmulx fscale mad sabd sqincd udot uxtb
// cnt fcvtzu fneg fsqrt mla scvtf sqinch umax uxth
// cpy fdiv fnmad fsub mls sdiv sqincp umin uxtw
// ------------------------------------------------------------------------- //
// Test compatibility with MOVPRFX instruction with BRK and HLT.
//
// Section 7.1.2 of the SVE Architecture Reference Manual Supplement:
// "it is permitted to use MOVPRFX to prefix an A64 BRK or HLT instruction"
movprfx z0, z1
// CHECK-INST: movprfx z0, z1
// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
hlt #1
// CHECK-INST: hlt #0x1
// CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
movprfx z0.d, p0/z, z1.d
// CHECK-INST: movprfx z0.d, p0/z, z1.d
// CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
hlt #1
// CHECK-INST: hlt #0x1
// CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
movprfx z0, z1
// CHECK-INST: movprfx z0, z1
// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
brk #1
// CHECK-INST: brk #0x1
// CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
movprfx z0.d, p0/z, z1.d
// CHECK-INST: movprfx z0.d, p0/z, z1.d
// CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
brk #1
// CHECK-INST: brk #0x1
// CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
// ------------------------------------------------------------------------- //
// Ensure we don't try to apply a prefix to subsequent instructions (upon success)
movprfx z0, z1
// CHECK-INST: movprfx z0, z1
// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
add z0.d, p0/m, z0.d, z1.d
// CHECK-INST: add z0.d, p0/m, z0.d, z1.d
// CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 c0 04 <unknown>
add z0.d, p0/m, z0.d, z1.d
// CHECK-INST: add z0.d, p0/m, z0.d, z1.d
// CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 c0 04 <unknown>

test/MC/AArch64/SVE/msb.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 ff 81 04 <unknown> // CHECK-UNKNOWN: e0 ff 81 04 <unknown>
msb z0.d, p7/m, z1.d, z31.d msb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d // CHECK-INST: msb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 ff c1 04 <unknown> // CHECK-UNKNOWN: e0 ff c1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
msb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 ff c1 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
msb z0.d, p7/m, z1.d, z31.d
// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d
// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 ff c1 04 <unknown>

test/MC/AArch64/SVE/mul-diagnostics.s

Show All 30 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
mul z0.b, p8/m, z0.b, z1.b mul z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
mul z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: mul z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/mul.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f d0 f0 25 <unknown> // CHECK-UNKNOWN: 1f d0 f0 25 <unknown>
mul z31.d, z31.d, #127 mul z31.d, z31.d, #127
// CHECK-INST: mul z31.d, z31.d, #127 // CHECK-INST: mul z31.d, z31.d, #127
// CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff cf f0 25 <unknown> // CHECK-UNKNOWN: ff cf f0 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
mul z0.d, p7/m, z0.d, z31.d
// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mul z0.d, p7/m, z0.d, z31.d
// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d0 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
mul z31.d, z31.d, #127
// CHECK-INST: mul z31.d, z31.d, #127
// CHECK-ENCODING: [0xff,0xcf,0xf0,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff cf f0 25 <unknown>

test/MC/AArch64/SVE/neg.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 97 04 <unknown> // CHECK-UNKNOWN: ff bf 97 04 <unknown>
neg z31.d, p7/m, z31.d neg z31.d, p7/m, z31.d
// CHECK-INST: neg z31.d, p7/m, z31.d // CHECK-INST: neg z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd7,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d7 04 <unknown> // CHECK-UNKNOWN: ff bf d7 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
neg z4.d, p7/m, z31.d
// CHECK-INST: neg z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d7 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
neg z4.d, p7/m, z31.d
// CHECK-INST: neg z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d7 04 <unknown>

test/MC/AArch64/SVE/not.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 42 00 25 <unknown> // CHECK-UNKNOWN: 00 42 00 25 <unknown>
not p15.b, p15/z, p15.b not p15.b, p15/z, p15.b
// CHECK-INST: not p15.b, p15/z, p15.b // CHECK-INST: not p15.b, p15/z, p15.b
// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 7f 0f 25 <unknown> // CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
not z4.d, p7/m, z31.d
// CHECK-INST: not z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf de 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
not z4.d, p7/m, z31.d
// CHECK-INST: not z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf de 04 <unknown>

test/MC/AArch64/SVE/orn-diagnostics.s

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Operation only has zeroing predicate behaviour (p0/z). // Operation only has zeroing predicate behaviour (p0/z).
orn p0.b, p0/m, p1.b, p2.b orn p0.b, p0/m, p1.b, p2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b // CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
orn z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: orn z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/orn.s

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 10 40 80 25 <unknown> // CHECK-UNKNOWN: 10 40 80 25 <unknown>
orn p15.b, p15/z, p15.b, p15.b orn p15.b, p15/z, p15.b, p15.b
// CHECK-INST: orn p15.b, p15/z, p15.b, p15.b // CHECK-INST: orn p15.b, p15/z, p15.b, p15.b
// CHECK-ENCODING: [0xff,0x7d,0x8f,0x25] // CHECK-ENCODING: [0xff,0x7d,0x8f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7d 8f 25 <unknown> // CHECK-UNKNOWN: ff 7d 8f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
orn z0.d, z0.d, #0x6
// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 03 05 <unknown>

test/MC/AArch64/SVE/orr-diagnostics.s

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Operation only has zeroing predicate behaviour (p0/z). // Operation only has zeroing predicate behaviour (p0/z).
orr p0.b, p0/m, p1.b, p2.b orr p0.b, p0/m, p1.b, p2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b // CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
orr z0.d, z0.d, #0x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: orr z0.d, z0.d, #0x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23.d, p0/z, z30.d
orr z23.d, z13.d, z8.d // should not use mov-alias
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
orr z23.d, z13.d, z8.d // should not use mov-alias
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
orr z0.d, z0.d, z0.d // should use mov-alias
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
orr z0.d, z0.d, z0.d // should use mov-alias
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/orr.s

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 80 25 <unknown> // CHECK-UNKNOWN: 00 40 80 25 <unknown>
orr p15.b, p15/z, p15.b, p15.b orr p15.b, p15/z, p15.b, p15.b
// CHECK-INST: mov p15.b, p15.b // CHECK-INST: mov p15.b, p15.b
// CHECK-ENCODING: [0xef,0x7d,0x8f,0x25] // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ef 7d 8f 25 <unknown> // CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
orr z4.d, p7/m, z4.d, z31.d
// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f d8 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
orr z4.d, p7/m, z4.d, z31.d
// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f d8 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
orr z0.d, z0.d, #0x6
// CHECK-INST: orr z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 03 05 <unknown>

test/MC/AArch64/SVE/orv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
orv h0, p8, z31.h orv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: orv h0, p8, z31.h // CHECK-NEXT: orv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
orv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
orv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: orv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/prfb-diagnostics.s

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfb #0, p8, [x0] prfb #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: prfb #0, p8, [x0] // CHECK-NEXT: prfb #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
prfb pldl1keep, p0, [x0, z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
prfb pldl1keep, p0, [x0, z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/prfd-diagnostics.s

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfd #0, p8, [x0] prfd #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: prfd #0, p8, [x0] // CHECK-NEXT: prfd #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
prfd pldl1keep, p0, [x0, z0.d, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
prfd pldl1keep, p0, [x0, z0.d, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/prfh-diagnostics.s

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfh #0, p8, [x0] prfh #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: prfh #0, p8, [x0] // CHECK-NEXT: prfh #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
prfh pldl1keep, p0, [x0, z0.d, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
prfh pldl1keep, p0, [x0, z0.d, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/prfw-diagnostics.s

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfw #0, p8, [x0] prfw #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: prfw #0, p8, [x0] // CHECK-NEXT: prfw #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z8.d, p3/z, z15.d
prfw #7, p3, [x13, z8.d, uxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z8, z15
prfw #7, p3, [x13, z8.d, uxtw #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21.d, p5/z, z28.d
prfw pldl3strm, p5, [x10, z21.d, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
prfw pldl3strm, p5, [x10, z21.d, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/rbit.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a7 05 <unknown> // CHECK-UNKNOWN: e0 9f a7 05 <unknown>
rbit z0.d, p7/m, z31.d rbit z0.d, p7/m, z31.d
// CHECK-INST: rbit z0.d, p7/m, z31.d // CHECK-INST: rbit z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e7 05 <unknown> // CHECK-UNKNOWN: e0 9f e7 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
rbit z0.d, p7/m, z31.d
// CHECK-INST: rbit z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e7 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
rbit z0.d, p7/m, z31.d
// CHECK-INST: rbit z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e7 05 <unknown>

test/MC/AArch64/SVE/rev-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
rev z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rev z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
rev z0.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rev z0.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/revb.s

Show All 18 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a4 05 <unknown> // CHECK-UNKNOWN: e0 9f a4 05 <unknown>
revb z0.d, p7/m, z31.d revb z0.d, p7/m, z31.d
// CHECK-INST: revb z0.d, p7/m, z31.d // CHECK-INST: revb z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e4 05 <unknown> // CHECK-UNKNOWN: e0 9f e4 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
revb z0.d, p7/m, z31.d
// CHECK-INST: revb z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e4 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
revb z0.d, p7/m, z31.d
// CHECK-INST: revb z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e4 05 <unknown>

test/MC/AArch64/SVE/revh.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a5 05 <unknown> // CHECK-UNKNOWN: e0 9f a5 05 <unknown>
revh z0.d, p7/m, z31.d revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d // CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown> // CHECK-UNKNOWN: e0 9f e5 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown>

test/MC/AArch64/SVE/revw.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
revw z0.d, p7/m, z31.d revw z0.d, p7/m, z31.d
// CHECK-INST: revw z0.d, p7/m, z31.d // CHECK-INST: revw z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e6 05 <unknown> // CHECK-UNKNOWN: e0 9f e6 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
revw z0.d, p7/m, z31.d
// CHECK-INST: revw z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e6 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
revw z0.d, p7/m, z31.d
// CHECK-INST: revw z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e6 05 <unknown>

test/MC/AArch64/SVE/sabd.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 8c 04 <unknown> // CHECK-UNKNOWN: ff 1f 8c 04 <unknown>
sabd z31.d, p7/m, z31.d, z31.d sabd z31.d, p7/m, z31.d, z31.d
// CHECK-INST: sabd z31.d, p7/m, z31.d, z31.d // CHECK-INST: sabd z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xcc,0x04] // CHECK-ENCODING: [0xff,0x1f,0xcc,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f cc 04 <unknown> // CHECK-UNKNOWN: ff 1f cc 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
sabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cc 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cc 04 <unknown>

test/MC/AArch64/SVE/saddv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
saddv d0, p8, z31.b saddv d0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: saddv d0, p8, z31.b // CHECK-NEXT: saddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.s, p7/z, z6.s
saddv d0, p7, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddv d0, p7, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
saddv d0, p7, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddv d0, p7, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/scvtf.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d0 65 <unknown> // CHECK-UNKNOWN: 00 a0 d0 65 <unknown>
scvtf z0.d, p0/m, z0.d scvtf z0.d, p0/m, z0.d
// CHECK-INST: scvtf z0.d, p0/m, z0.d // CHECK-INST: scvtf z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd6,0x65] // CHECK-ENCODING: [0x00,0xa0,0xd6,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d6 65 <unknown> // CHECK-UNKNOWN: 00 a0 d6 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
scvtf z5.d, p0/m, z0.d
// CHECK-INST: scvtf z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 d6 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
scvtf z5.d, p0/m, z0.d
// CHECK-INST: scvtf z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 d6 65 <unknown>

test/MC/AArch64/SVE/sdiv.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 94 04 <unknown> // CHECK-UNKNOWN: e0 1f 94 04 <unknown>
sdiv z0.d, p7/m, z0.d, z31.d sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d4 04 <unknown> // CHECK-UNKNOWN: e0 1f d4 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d4 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d4 04 <unknown>

test/MC/AArch64/SVE/sdivr.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 96 04 <unknown> // CHECK-UNKNOWN: e0 1f 96 04 <unknown>
sdivr z0.d, p7/m, z0.d, z31.d sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d6 04 <unknown> // CHECK-UNKNOWN: e0 1f d6 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d6 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d6 04 <unknown>

test/MC/AArch64/SVE/sdot-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sdot z0.d, z1.h, z15.h[-1] // CHECK-NEXT: sdot z0.d, z1.h, z15.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sdot z0.d, z1.h, z15.h[2] sdot z0.d, z1.h, z15.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sdot z0.d, z1.h, z15.h[2] // CHECK-NEXT: sdot z0.d, z1.h, z15.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sdot z0.d, z1.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sdot z0.d, z1.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sdot z0.d, z1.h, z15.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sdot z0.d, z1.h, z15.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sdot.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 bf 44 <unknown> // CHECK-UNKNOWN: 20 00 bf 44 <unknown>
sdot z0.d, z1.h, z15.h[1] sdot z0.d, z1.h, z15.h[1]
// CHECK-INST: sdot z0.d, z1.h, z15.h[1] // CHECK-INST: sdot z0.d, z1.h, z15.h[1]
// CHECK-ENCODING: [0x20,0x00,0xff,0x44] // CHECK-ENCODING: [0x20,0x00,0xff,0x44]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 ff 44 <unknown> // CHECK-UNKNOWN: 20 00 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sdot z0.d, z1.h, z31.h
// CHECK-INST: sdot z0.d, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x00,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 df 44 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sdot z0.d, z1.h, z15.h[1]
// CHECK-INST: sdot z0.d, z1.h, z15.h[1]
// CHECK-ENCODING: [0x20,0x00,0xff,0x44]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 00 ff 44 <unknown>

test/MC/AArch64/SVE/sel-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z28.b, p7/z, z30.b
sel z28.b, p7, z13.b, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sel z28.b, p7, z13.b, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
sel z23.b, p11, z13.b, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sel z23.b, p11, z13.b, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/smax-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
smax z0.b, z0.b, #-129 smax z0.b, z0.b, #-129
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smax z0.b, z0.b, #-129 // CHECK-NEXT: smax z0.b, z0.b, #-129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smax z31.b, z31.b, #128 smax z31.b, z31.b, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smax z31.b, z31.b, #128 // CHECK-NEXT: smax z31.b, z31.b, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smax z0.b, p8/m, z0.b, z0.b smax z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
smax z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smax z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/smax.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 88 04 <unknown> // CHECK-UNKNOWN: ff 1f 88 04 <unknown>
smax z31.d, p7/m, z31.d, z31.d smax z31.d, p7/m, z31.d, z31.d
// CHECK-INST: smax z31.d, p7/m, z31.d, z31.d // CHECK-INST: smax z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xc8,0x04] // CHECK-ENCODING: [0xff,0x1f,0xc8,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f c8 04 <unknown> // CHECK-UNKNOWN: ff 1f c8 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
smax z4.d, p7/m, z4.d, z31.d
// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f c8 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
smax z4.d, p7/m, z4.d, z31.d
// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f c8 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
smax z31.d, z31.d, #127
// CHECK-INST: smax z31.d, z31.d, #127
// CHECK-ENCODING: [0xff,0xcf,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff cf e8 25 <unknown>

test/MC/AArch64/SVE/smaxv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
smaxv h0, p8, z31.h smaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: smaxv h0, p8, z31.h // CHECK-NEXT: smaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
smaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
smaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/smin-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
smin z0.b, z0.b, #-129 smin z0.b, z0.b, #-129
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smin z0.b, z0.b, #-129 // CHECK-NEXT: smin z0.b, z0.b, #-129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smin z31.b, z31.b, #128 smin z31.b, z31.b, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smin z31.b, z31.b, #128 // CHECK-NEXT: smin z31.b, z31.b, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smin z0.b, p8/m, z0.b, z0.b smin z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
smin z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smin z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/smin.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 8a 04 <unknown> // CHECK-UNKNOWN: ff 1f 8a 04 <unknown>
smin z31.d, p7/m, z31.d, z31.d smin z31.d, p7/m, z31.d, z31.d
// CHECK-INST: smin z31.d, p7/m, z31.d, z31.d // CHECK-INST: smin z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xca,0x04] // CHECK-ENCODING: [0xff,0x1f,0xca,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f ca 04 <unknown> // CHECK-UNKNOWN: ff 1f ca 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
smin z4.d, p7/m, z4.d, z31.d
// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f ca 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
smin z4.d, p7/m, z4.d, z31.d
// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f ca 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
smin z31.d, z31.d, #127
// CHECK-INST: smin z31.d, z31.d, #127
// CHECK-ENCODING: [0xff,0xcf,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff cf ea 25 <unknown>

test/MC/AArch64/SVE/sminv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sminv h0, p8, z31.h sminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sminv h0, p8, z31.h // CHECK-NEXT: sminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
sminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/smulh.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 92 04 <unknown> // CHECK-UNKNOWN: e0 1f 92 04 <unknown>
smulh z0.d, p7/m, z0.d, z31.d smulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d2 04 <unknown> // CHECK-UNKNOWN: e0 1f d2 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
smulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d2 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
smulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d2 04 <unknown>

test/MC/AArch64/SVE/splice-diagnostics.s

Show All 19 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
splice z0.b, p8, z0.b, z1.b splice z0.b, p8, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: splice z0.b, p8, z0.b, z1.b // CHECK-NEXT: splice z0.b, p8, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z4.d, p7/z, z6.d
splice z4.d, p7, z4.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: splice z4.d, p7, z4.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/splice.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f ac 05 <unknown> // CHECK-UNKNOWN: ff 9f ac 05 <unknown>
splice z31.d, p7, z31.d, z31.d splice z31.d, p7, z31.d, z31.d
// CHECK-INST: splice z31.d, p7, z31.d, z31.d // CHECK-INST: splice z31.d, p7, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x9f,0xec,0x05] // CHECK-ENCODING: [0xff,0x9f,0xec,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f ec 05 <unknown> // CHECK-UNKNOWN: ff 9f ec 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
splice z4.d, p7, z4.d, z31.d
// CHECK-INST: splice z4.d, p7, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x9f,0xec,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 9f ec 05 <unknown>

test/MC/AArch64/SVE/sqadd-diagnostics.s

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sqadd z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: sqadd z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqadd z0.d, z0.d, #65536 sqadd z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sqadd z0.d, z0.d, #65536 // CHECK-NEXT: sqadd z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqadd z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqadd z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqadd z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqadd z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
sqadd z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqadd z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqadd.s

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e4 25 <unknown> // CHECK-UNKNOWN: ff ff e4 25 <unknown>
sqadd z31.d, z31.d, #65280 sqadd z31.d, z31.d, #65280
// CHECK-INST: sqadd z31.d, z31.d, #65280 // CHECK-INST: sqadd z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe4,0x25] // CHECK-ENCODING: [0xff,0xff,0xe4,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e4 25 <unknown> // CHECK-UNKNOWN: ff ff e4 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqadd z31.d, z31.d, #65280
// CHECK-INST: sqadd z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe4,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e4 25 <unknown>

test/MC/AArch64/SVE/sqdecd-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecd x0, #-1 // CHECK-NEXT: sqdecd x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecd x0, #32 sqdecd x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecd x0, #32 // CHECK-NEXT: sqdecd x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdecd z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecd z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdecd z0.d, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecd z0.d, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdecd z0.d, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecd z0.d, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqdecd.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 fb f0 04 <unknown> // CHECK-UNKNOWN: 60 fb f0 04 <unknown>
sqdecd x0, #28 sqdecd x0, #28
// CHECK-INST: sqdecd x0, #28 // CHECK-INST: sqdecd x0, #28
// CHECK-ENCODING: [0x80,0xfb,0xf0,0x04] // CHECK-ENCODING: [0x80,0xfb,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 fb f0 04 <unknown> // CHECK-UNKNOWN: 80 fb f0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecd z0.d
// CHECK-INST: sqdecd z0.d
// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecd z0.d, pow2, mul #16
// CHECK-INST: sqdecd z0.d, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecd z0.d, pow2
// CHECK-INST: sqdecd z0.d, pow2
// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>

test/MC/AArch64/SVE/sqdech-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdech x0, #-1 // CHECK-NEXT: sqdech x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdech x0, #32 sqdech x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdech x0, #32 // CHECK-NEXT: sqdech x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
sqdech z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdech z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
sqdech z0.h, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdech z0.h, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
sqdech z0.h, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdech z0.h, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqdech.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 fb 70 04 <unknown> // CHECK-UNKNOWN: 60 fb 70 04 <unknown>
sqdech x0, #28 sqdech x0, #28
// CHECK-INST: sqdech x0, #28 // CHECK-INST: sqdech x0, #28
// CHECK-ENCODING: [0x80,0xfb,0x70,0x04] // CHECK-ENCODING: [0x80,0xfb,0x70,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 fb 70 04 <unknown> // CHECK-UNKNOWN: 80 fb 70 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdech z0.h
// CHECK-INST: sqdech z0.h
// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdech z0.h, pow2, mul #16
// CHECK-INST: sqdech z0.h, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc8,0x6f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 6f 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdech z0.h, pow2
// CHECK-INST: sqdech z0.h, pow2
// CHECK-ENCODING: [0x00,0xc8,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 60 04 <unknown>

test/MC/AArch64/SVE/sqdecp-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sqdecp x0, p0/m // CHECK-NEXT: sqdecp x0, p0/m
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecp x0, p0.q sqdecp x0, p0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sqdecp x0, p0.q // CHECK-NEXT: sqdecp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdecp z0.d, p0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecp z0.d, p0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqdecp.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown> // CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.d, p0 sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0 // CHECK-INST: sqdecp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xea,0x25] // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown> // CHECK-UNKNOWN: 00 80 ea 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>

test/MC/AArch64/SVE/sqdecw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecw x0, #-1 // CHECK-NEXT: sqdecw x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecw x0, #32 sqdecw x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecw x0, #32 // CHECK-NEXT: sqdecw x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
sqdecw z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecw z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqdecw z0.s, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecw z0.s, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqdecw z0.s, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdecw z0.s, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqdecw.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 fb b0 04 <unknown> // CHECK-UNKNOWN: 60 fb b0 04 <unknown>
sqdecw x0, #28 sqdecw x0, #28
// CHECK-INST: sqdecw x0, #28 // CHECK-INST: sqdecw x0, #28
// CHECK-ENCODING: [0x80,0xfb,0xb0,0x04] // CHECK-ENCODING: [0x80,0xfb,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 fb b0 04 <unknown> // CHECK-UNKNOWN: 80 fb b0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecw z0.s
// CHECK-INST: sqdecw z0.s
// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecw z0.s, pow2, mul #16
// CHECK-INST: sqdecw z0.s, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc8,0xaf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 af 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecw z0.s, pow2
// CHECK-INST: sqdecw z0.s, pow2
// CHECK-ENCODING: [0x00,0xc8,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c8 a0 04 <unknown>

test/MC/AArch64/SVE/sqincd-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqincd x0, #-1 // CHECK-NEXT: sqincd x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincd x0, #32 sqincd x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqincd x0, #32 // CHECK-NEXT: sqincd x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqincd z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincd z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqincd z0.d, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincd z0.d, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqincd z0.d, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincd z0.d, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqincd.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f3 f0 04 <unknown> // CHECK-UNKNOWN: 60 f3 f0 04 <unknown>
sqincd x0, #28 sqincd x0, #28
// CHECK-INST: sqincd x0, #28 // CHECK-INST: sqincd x0, #28
// CHECK-ENCODING: [0x80,0xf3,0xf0,0x04] // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f3 f0 04 <unknown> // CHECK-UNKNOWN: 80 f3 f0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincd z0.d
// CHECK-INST: sqincd z0.d
// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincd z0.d, pow2, mul #16
// CHECK-INST: sqincd z0.d, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 ef 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincd z0.d, pow2
// CHECK-INST: sqincd z0.d, pow2
// CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 e0 04 <unknown>

test/MC/AArch64/SVE/sqinch-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqinch x0, #-1 // CHECK-NEXT: sqinch x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqinch x0, #32 sqinch x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqinch x0, #32 // CHECK-NEXT: sqinch x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
sqinch z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqinch z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
sqinch z0.h, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqinch z0.h, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
sqinch z0.h, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqinch z0.h, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqinch.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f3 70 04 <unknown> // CHECK-UNKNOWN: 60 f3 70 04 <unknown>
sqinch x0, #28 sqinch x0, #28
// CHECK-INST: sqinch x0, #28 // CHECK-INST: sqinch x0, #28
// CHECK-ENCODING: [0x80,0xf3,0x70,0x04] // CHECK-ENCODING: [0x80,0xf3,0x70,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f3 70 04 <unknown> // CHECK-UNKNOWN: 80 f3 70 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqinch z0.h
// CHECK-INST: sqinch z0.h
// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqinch z0.h, pow2, mul #16
// CHECK-INST: sqinch z0.h, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc0,0x6f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 6f 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqinch z0.h, pow2
// CHECK-INST: sqinch z0.h, pow2
// CHECK-ENCODING: [0x00,0xc0,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 60 04 <unknown>

test/MC/AArch64/SVE/sqincp-diagnostics.s

Show All 40 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: uqdecp x0, p0/m // CHECK-NEXT: uqdecp x0, p0/m
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecp x0, p0.q uqdecp x0, p0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: uqdecp x0, p0.q // CHECK-NEXT: uqdecp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqincp z0.d, p0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincp z0.d, p0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqincp.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown> // CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.d, p0 sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0 // CHECK-INST: sqincp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25] // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown> // CHECK-UNKNOWN: 00 80 e8 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>

test/MC/AArch64/SVE/sqincw-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqincw x0, #-1 // CHECK-NEXT: sqincw x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincw x0, #32 sqincw x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqincw x0, #32 // CHECK-NEXT: sqincw x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
sqincw z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincw z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqincw z0.s, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincw z0.s, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqincw z0.s, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqincw z0.s, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqincw.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f3 b0 04 <unknown> // CHECK-UNKNOWN: 60 f3 b0 04 <unknown>
sqincw x0, #28 sqincw x0, #28
// CHECK-INST: sqincw x0, #28 // CHECK-INST: sqincw x0, #28
// CHECK-ENCODING: [0x80,0xf3,0xb0,0x04] // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f3 b0 04 <unknown> // CHECK-UNKNOWN: 80 f3 b0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincw z0.s
// CHECK-INST: sqincw z0.s
// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincw z0.s, pow2, mul #16
// CHECK-INST: sqincw z0.s, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincw z0.s, pow2
// CHECK-INST: sqincw z0.s, pow2
// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>

test/MC/AArch64/SVE/sqsub-diagnostics.s

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sqsub z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: sqsub z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqsub z0.d, z0.d, #65536 sqsub z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sqsub z0.d, z0.d, #65536 // CHECK-NEXT: sqsub z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqsub z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqsub z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqsub z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqsub z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
sqsub z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqsub z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sqsub.s

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e6 25 <unknown> // CHECK-UNKNOWN: ff ff e6 25 <unknown>
sqsub z31.d, z31.d, #65280 sqsub z31.d, z31.d, #65280
// CHECK-INST: sqsub z31.d, z31.d, #65280 // CHECK-INST: sqsub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe6,0x25] // CHECK-ENCODING: [0xff,0xff,0xe6,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e6 25 <unknown> // CHECK-UNKNOWN: ff ff e6 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqsub z31.d, z31.d, #65280
// CHECK-INST: sqsub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe6,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e6 25 <unknown>

test/MC/AArch64/SVE/st1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: st1b z0.d, p0, [z0.d, #-1] // CHECK-NEXT: st1b z0.d, p0, [z0.d, #-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z0.d, p0, [z0.d, #32] st1b z0.d, p0, [z0.d, #32]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
// CHECK-NEXT: st1b z0.d, p0, [z0.d, #32] // CHECK-NEXT: st1b z0.d, p0, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
st1b { z31.d }, p7, [z31.d, #31]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
st1b { z31.d }, p7, [z31.d, #31]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: st1d z0.d, p0, [z0.d, #256] // CHECK-NEXT: st1d z0.d, p0, [z0.d, #256]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d z0.d, p0, [z0.d, #3] st1d z0.d, p0, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
// CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
st1d { z31.d }, p7, [z31.d, #248]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
st1d { z31.d }, p7, [z31.d, #248]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: st1h z0.d, p0, [z0.d, #64] // CHECK-NEXT: st1h z0.d, p0, [z0.d, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z0.d, p0, [z0.d, #3] st1h z0.d, p0, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: st1h z0.d, p0, [z0.d, #3] // CHECK-NEXT: st1h z0.d, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
st1h { z31.d }, p7, [z31.d, #62]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
st1h { z31.d }, p7, [z31.d, #62]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: st1w z0.d, p0, [z0.d, #128] // CHECK-NEXT: st1w z0.d, p0, [z0.d, #128]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z0.d, p0, [z0.d, #3] st1w z0.d, p0, [z0.d, #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
// CHECK-NEXT: st1w z0.d, p0, [z0.d, #3] // CHECK-NEXT: st1w z0.d, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
st1w { z31.d }, p7, [z31.d, #124]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
st1w { z31.d }, p7, [z31.d, #124]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st2b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0] // CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st2b { v0.2d, v1.2d }, p0, [x0] st2b { v0.2d, v1.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0] // CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st2d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0] // CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st2d { v0.2d, v1.2d }, p0, [x0] st2d { v0.2d, v1.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0] // CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st2h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0] // CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st2h { v0.2d, v1.2d }, p0, [x0] st2h { v0.2d, v1.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0] // CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st2w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0] // CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st2w { v0.2d, v1.2d }, p0, [x0] st2w { v0.2d, v1.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0] // CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st3b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0] // CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st3d-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0] // CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st3h-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0] // CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st3w-diagnostics.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0] // CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st4b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0] // CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.b, p5/z, z28.b
st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st4d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0] // CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.d, p5/z, z28.d
st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st4h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0] // CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st4w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0] // CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.s, p5/z, z28.s
st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/stnt1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1b { z1.b, z2.b }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1b { z1.b, z2.b }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { v0.2d }, p0, [x1, #1, MUL VL] stnt1b { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1b { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1b { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
stnt1b { z0.b }, p0, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1b { z0.b }, p0, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/stnt1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1d { z1.d, z2.d }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1d { z1.d, z2.d }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { v0.2d }, p0, [x1, #1, MUL VL] stnt1d { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1d { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1d { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/stnt1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { v0.2d }, p0, [x1, #1, MUL VL] stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
stnt1h { z0.h }, p0, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1h { z0.h }, p0, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/stnt1w-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1w { z1.s, z2.s }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1w { z1.s, z2.s }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { v0.2d }, p0, [x1, #1, MUL VL] stnt1w { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: stnt1w { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NEXT: stnt1w { v0.2d }, p0, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
stnt1w { z0.s }, p0, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1w { z0.s }, p0, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sub-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sub z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: sub z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sub z0.d, z0.d, #65536 sub z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: sub z0.d, z0.d, #65536 // CHECK-NEXT: sub z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sub z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sub z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.s, p0/z, z6.s
sub z31.s, z31.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sub z31.s, z31.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sub z31.s, z31.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sub z31.s, z31.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sub.s

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// CHECK-UNKNOWN: ff ff e1 25 <unknown> // CHECK-UNKNOWN: ff ff e1 25 <unknown>
sub z31.d, z31.d, #65280 sub z31.d, z31.d, #65280
// CHECK-INST: sub z31.d, z31.d, #65280 // CHECK-INST: sub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe1,0x25] // CHECK-ENCODING: [0xff,0xff,0xe1,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e1 25 <unknown> // CHECK-UNKNOWN: ff ff e1 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z23.b, p3/z, z30.b
// CHECK-INST: movprfx z23.b, p3/z, z30.b
// CHECK-ENCODING: [0xd7,0x2f,0x10,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: d7 2f 10 04 <unknown>
sub z23.b, p3/m, z23.b, z13.b
// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b
// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 0d 01 04 <unknown>
movprfx z23, z30
// CHECK-INST: movprfx z23, z30
// CHECK-ENCODING: [0xd7,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: d7 bf 20 04 <unknown>
sub z23.b, p3/m, z23.b, z13.b
// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b
// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 0d 01 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sub z31.d, z31.d, #65280
// CHECK-INST: sub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe1,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e1 25 <unknown>

test/MC/AArch64/SVE/subr-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: subr z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.d, z0.d, #65536 subr z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.d, z0.d, #65536 // CHECK-NEXT: subr z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
subr z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: subr z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/subr.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e3 25 <unknown> // CHECK-UNKNOWN: ff ff e3 25 <unknown>
subr z31.d, z31.d, #65280 subr z31.d, z31.d, #65280
// CHECK-INST: subr z31.d, z31.d, #65280 // CHECK-INST: subr z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe3,0x25] // CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e3 25 <unknown> // CHECK-UNKNOWN: ff ff e3 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
subr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x00,0xc3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 00 c3 04 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
subr z5.d, p0/m, z5.d, z0.d
// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d
// CHECK-ENCODING: [0x05,0x00,0xc3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 00 c3 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
subr z31.d, z31.d, #65280
// CHECK-INST: subr z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e3 25 <unknown>

test/MC/AArch64/SVE/sunpkhi-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sunpkhi z0.s, z0.b // CHECK-NEXT: sunpkhi z0.s, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sunpkhi z0.d, z0.h sunpkhi z0.d, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sunpkhi z0.d, z0.h // CHECK-NEXT: sunpkhi z0.d, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sunpkhi z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sunpkhi z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sunpkhi z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sunpkhi z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sunpklo-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sunpklo z0.s, z0.b // CHECK-NEXT: sunpklo z0.s, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sunpklo z0.d, z0.h sunpklo z0.d, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sunpklo z0.d, z0.h // CHECK-NEXT: sunpklo z0.d, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sunpklo z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sunpklo z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sunpklo z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sunpklo z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/sxtb.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 90 04 <unknown> // CHECK-UNKNOWN: ff bf 90 04 <unknown>
sxtb z31.d, p7/m, z31.d sxtb z31.d, p7/m, z31.d
// CHECK-INST: sxtb z31.d, p7/m, z31.d // CHECK-INST: sxtb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd0,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d0 04 <unknown> // CHECK-UNKNOWN: ff bf d0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
sxtb z4.d, p7/m, z31.d
// CHECK-INST: sxtb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d0 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sxtb z4.d, p7/m, z31.d
// CHECK-INST: sxtb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d0 04 <unknown>

test/MC/AArch64/SVE/sxth.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 92 04 <unknown> // CHECK-UNKNOWN: ff bf 92 04 <unknown>
sxth z31.d, p7/m, z31.d sxth z31.d, p7/m, z31.d
// CHECK-INST: sxth z31.d, p7/m, z31.d // CHECK-INST: sxth z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd2,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d2 04 <unknown> // CHECK-UNKNOWN: ff bf d2 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
sxth z4.d, p7/m, z31.d
// CHECK-INST: sxth z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d2 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sxth z4.d, p7/m, z31.d
// CHECK-INST: sxth z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d2 04 <unknown>

test/MC/AArch64/SVE/sxtw.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d4 04 <unknown> // CHECK-UNKNOWN: 00 a0 d4 04 <unknown>
sxtw z31.d, p7/m, z31.d sxtw z31.d, p7/m, z31.d
// CHECK-INST: sxtw z31.d, p7/m, z31.d // CHECK-INST: sxtw z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd4,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d4 04 <unknown> // CHECK-UNKNOWN: ff bf d4 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
sxtw z4.d, p7/m, z31.d
// CHECK-INST: sxtw z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d4 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sxtw z4.d, p7/m, z31.d
// CHECK-INST: sxtw z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d4 04 <unknown>

test/MC/AArch64/SVE/tbl-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
tbl z0.h, z0.h, z0.b tbl z0.h, z0.h, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: tbl z0.h, z0.h, z0.b // CHECK-NEXT: tbl z0.h, z0.h, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl { z0.h }, z0.h, z0.h tbl { z0.h }, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: tbl { z0.h }, z0.h, z0.h // CHECK-NEXT: tbl { z0.h }, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
tbl z31.d, { z31.d }, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
tbl z31.d, { z31.d }, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/trn1-diagnostics.s

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// CHECK-NEXT: trn1 z1.s, z2.s, p3.s // CHECK-NEXT: trn1 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
trn1 p1.s, p2.s, z3.s trn1 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: trn1 p1.s, p2.s, z3.s // CHECK-NEXT: trn1 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
trn1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: trn1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
trn1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: trn1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/trn2-diagnostics.s

Show All 35 Lines
// CHECK-NEXT: trn2 z1.s, z2.s, p3.s // CHECK-NEXT: trn2 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
trn2 p1.s, p2.s, z3.s trn2 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: trn2 p1.s, p2.s, z3.s // CHECK-NEXT: trn2 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
trn2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: trn2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
trn2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: trn2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uabd.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 8d 04 <unknown> // CHECK-UNKNOWN: ff 1f 8d 04 <unknown>
uabd z31.d, p7/m, z31.d, z31.d uabd z31.d, p7/m, z31.d, z31.d
// CHECK-INST: uabd z31.d, p7/m, z31.d, z31.d // CHECK-INST: uabd z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xcd,0x04] // CHECK-ENCODING: [0xff,0x1f,0xcd,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f cd 04 <unknown> // CHECK-UNKNOWN: ff 1f cd 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
uabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cd 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
uabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cd 04 <unknown>

test/MC/AArch64/SVE/uaddv-diagnostics.s

Show All 20 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
uaddv d0, p8, z31.b uaddv d0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uaddv d0, p8, z31.b // CHECK-NEXT: uaddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
uaddv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uaddv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ucvtf.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d1 65 <unknown> // CHECK-UNKNOWN: 00 a0 d1 65 <unknown>
ucvtf z0.d, p0/m, z0.d ucvtf z0.d, p0/m, z0.d
// CHECK-INST: ucvtf z0.d, p0/m, z0.d // CHECK-INST: ucvtf z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd7,0x65] // CHECK-ENCODING: [0x00,0xa0,0xd7,0x65]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d7 65 <unknown> // CHECK-UNKNOWN: 00 a0 d7 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
ucvtf z5.d, p0/m, z0.d
// CHECK-INST: ucvtf z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 d7 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
ucvtf z5.d, p0/m, z0.d
// CHECK-INST: ucvtf z5.d, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 a0 d7 65 <unknown>

test/MC/AArch64/SVE/udiv.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 95 04 <unknown> // CHECK-UNKNOWN: e0 1f 95 04 <unknown>
udiv z0.d, p7/m, z0.d, z31.d udiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d5 04 <unknown> // CHECK-UNKNOWN: e0 1f d5 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
udiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d5 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
udiv z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d5 04 <unknown>

test/MC/AArch64/SVE/udivr.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 97 04 <unknown> // CHECK-UNKNOWN: e0 1f 97 04 <unknown>
udivr z0.d, p7/m, z0.d, z31.d udivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d7 04 <unknown> // CHECK-UNKNOWN: e0 1f d7 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
udivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d7 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
udivr z0.d, p7/m, z0.d, z31.d
// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d7 04 <unknown>

test/MC/AArch64/SVE/udot-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: udot z0.d, z1.h, z15.h[-1] // CHECK-NEXT: udot z0.d, z1.h, z15.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
udot z0.d, z1.h, z15.h[2] udot z0.d, z1.h, z15.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: udot z0.d, z1.h, z15.h[2] // CHECK-NEXT: udot z0.d, z1.h, z15.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
udot z0.d, z1.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: udot z0.d, z1.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
udot z0.d, z1.h, z15.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: udot z0.d, z1.h, z15.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/udot.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 bf 44 <unknown> // CHECK-UNKNOWN: 20 04 bf 44 <unknown>
udot z0.d, z1.h, z15.h[1] udot z0.d, z1.h, z15.h[1]
// CHECK-INST: udot z0.d, z1.h, z15.h[1] // CHECK-INST: udot z0.d, z1.h, z15.h[1]
// CHECK-ENCODING: [0x20,0x04,0xff,0x44] // CHECK-ENCODING: [0x20,0x04,0xff,0x44]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 ff 44 <unknown> // CHECK-UNKNOWN: 20 04 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
udot z0.d, z1.h, z31.h
// CHECK-INST: udot z0.d, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x04,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 df 44 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
udot z0.d, z1.h, z15.h[1]
// CHECK-INST: udot z0.d, z1.h, z15.h[1]
// CHECK-ENCODING: [0x20,0x04,0xff,0x44]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 04 ff 44 <unknown>

test/MC/AArch64/SVE/umax-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
umax z0.b, z0.b, #-1 umax z0.b, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umax z0.b, z0.b, #-1 // CHECK-NEXT: umax z0.b, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umax z31.b, z31.b, #256 umax z31.b, z31.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umax z31.b, z31.b, #256 // CHECK-NEXT: umax z31.b, z31.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umax z0.b, p8/m, z0.b, z0.b umax z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b
umax z31.b, z31.b, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umax z31.b, z31.b, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/umax.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 89 04 <unknown> // CHECK-UNKNOWN: ff 1f 89 04 <unknown>
umax z31.d, p7/m, z31.d, z31.d umax z31.d, p7/m, z31.d, z31.d
// CHECK-INST: umax z31.d, p7/m, z31.d, z31.d // CHECK-INST: umax z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xc9,0x04] // CHECK-ENCODING: [0xff,0x1f,0xc9,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f c9 04 <unknown> // CHECK-UNKNOWN: ff 1f c9 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
umax z4.d, p7/m, z4.d, z31.d
// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f c9 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
umax z4.d, p7/m, z4.d, z31.d
// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f c9 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
umax z31.b, z31.b, #255
// CHECK-INST: umax z31.b, z31.b, #255
// CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df 29 25 <unknown>

test/MC/AArch64/SVE/umaxv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
umaxv h0, p8, z31.h umaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: umaxv h0, p8, z31.h // CHECK-NEXT: umaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
umaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
umaxv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umaxv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/umin-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
umin z0.b, z0.b, #-1 umin z0.b, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umin z0.b, z0.b, #-1 // CHECK-NEXT: umin z0.b, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umin z31.b, z31.b, #256 umin z31.b, z31.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umin z31.b, z31.b, #256 // CHECK-NEXT: umin z31.b, z31.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umin z0.b, p8/m, z0.b, z0.b umin z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b
umin z31.b, z31.b, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umin z31.b, z31.b, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/umin.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 8b 04 <unknown> // CHECK-UNKNOWN: ff 1f 8b 04 <unknown>
umin z31.d, p7/m, z31.d, z31.d umin z31.d, p7/m, z31.d, z31.d
// CHECK-INST: umin z31.d, p7/m, z31.d, z31.d // CHECK-INST: umin z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xcb,0x04] // CHECK-ENCODING: [0xff,0x1f,0xcb,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f cb 04 <unknown> // CHECK-UNKNOWN: ff 1f cb 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
umin z4.d, p7/m, z4.d, z31.d
// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cb 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
umin z4.d, p7/m, z4.d, z31.d
// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 1f cb 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
umin z31.b, z31.b, #255
// CHECK-INST: umin z31.b, z31.b, #255
// CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df 2b 25 <unknown>

test/MC/AArch64/SVE/uminv-diagnostics.s

Show All 25 Lines
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
uminv h0, p8, z31.h uminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uminv h0, p8, z31.h // CHECK-NEXT: uminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d
uminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uminv d0, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uminv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/umulh.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f 93 04 <unknown> // CHECK-UNKNOWN: e0 1f 93 04 <unknown>
umulh z0.d, p7/m, z0.d, z31.d umulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d3 04 <unknown> // CHECK-UNKNOWN: e0 1f d3 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
umulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d3 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
umulh z0.d, p7/m, z0.d, z31.d
// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 1f d3 04 <unknown>

test/MC/AArch64/SVE/uqadd-diagnostics.s

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: uqadd z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: uqadd z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqadd z0.d, z0.d, #65536 uqadd z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: uqadd z0.d, z0.d, #65536 // CHECK-NEXT: uqadd z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uqadd z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqadd z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqadd z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqadd z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
uqadd z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqadd z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqadd.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e5 25 <unknown> // CHECK-UNKNOWN: ff ff e5 25 <unknown>
uqadd z31.d, z31.d, #65280 uqadd z31.d, z31.d, #65280
// CHECK-INST: uqadd z31.d, z31.d, #65280 // CHECK-INST: uqadd z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe5,0x25] // CHECK-ENCODING: [0xff,0xff,0xe5,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e5 25 <unknown> // CHECK-UNKNOWN: ff ff e5 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqadd z31.d, z31.d, #65280
// CHECK-INST: uqadd z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe5,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e5 25 <unknown>

test/MC/AArch64/SVE/uqdecd-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdecd x0, #-1 // CHECK-NEXT: uqdecd x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecd x0, #32 uqdecd x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdecd x0, #32 // CHECK-NEXT: uqdecd x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uqdecd z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecd z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqdecd z0.d, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecd z0.d, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqdecd z0.d, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecd z0.d, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqdecd.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 ff f0 04 <unknown> // CHECK-UNKNOWN: 60 ff f0 04 <unknown>
uqdecd x0, #28 uqdecd x0, #28
// CHECK-INST: uqdecd x0, #28 // CHECK-INST: uqdecd x0, #28
// CHECK-ENCODING: [0x80,0xff,0xf0,0x04] // CHECK-ENCODING: [0x80,0xff,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 ff f0 04 <unknown> // CHECK-UNKNOWN: 80 ff f0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecd z0.d
// CHECK-INST: uqdecd z0.d
// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecd z0.d, pow2, mul #16
// CHECK-INST: uqdecd z0.d, pow2, mul #16
// CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc ef 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecd z0.d, pow2
// CHECK-INST: uqdecd z0.d, pow2
// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc e0 04 <unknown>

test/MC/AArch64/SVE/uqdech-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdech x0, #-1 // CHECK-NEXT: uqdech x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdech x0, #32 uqdech x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdech x0, #32 // CHECK-NEXT: uqdech x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
uqdech z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdech z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
uqdech z0.h, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdech z0.h, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
uqdech z0.h, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdech z0.h, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqdech.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 ff 70 04 <unknown> // CHECK-UNKNOWN: 60 ff 70 04 <unknown>
uqdech x0, #28 uqdech x0, #28
// CHECK-INST: uqdech x0, #28 // CHECK-INST: uqdech x0, #28
// CHECK-ENCODING: [0x80,0xff,0x70,0x04] // CHECK-ENCODING: [0x80,0xff,0x70,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 ff 70 04 <unknown> // CHECK-UNKNOWN: 80 ff 70 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdech z0.h
// CHECK-INST: uqdech z0.h
// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdech z0.h, pow2, mul #16
// CHECK-INST: uqdech z0.h, pow2, mul #16
// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdech z0.h, pow2
// CHECK-INST: uqdech z0.h, pow2
// CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc 60 04 <unknown>

test/MC/AArch64/SVE/uqdecp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uqdecp z0.d, p0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecp z0.d, p0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqdecp.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown> // CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.d, p0 uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0 // CHECK-INST: uqdecp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25] // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown> // CHECK-UNKNOWN: 00 80 eb 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>

test/MC/AArch64/SVE/uqdecw-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdecw x0, #-1 // CHECK-NEXT: uqdecw x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecw x0, #32 uqdecw x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqdecw x0, #32 // CHECK-NEXT: uqdecw x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
uqdecw z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecw z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqdecw z0.s, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecw z0.s, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqdecw z0.s, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqdecw z0.s, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqdecw.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 ff b0 04 <unknown> // CHECK-UNKNOWN: 60 ff b0 04 <unknown>
uqdecw x0, #28 uqdecw x0, #28
// CHECK-INST: uqdecw x0, #28 // CHECK-INST: uqdecw x0, #28
// CHECK-ENCODING: [0x80,0xff,0xb0,0x04] // CHECK-ENCODING: [0x80,0xff,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 ff b0 04 <unknown> // CHECK-UNKNOWN: 80 ff b0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecw z0.s
// CHECK-INST: uqdecw z0.s
// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecw z0.s, pow2, mul #16
// CHECK-INST: uqdecw z0.s, pow2, mul #16
// CHECK-ENCODING: [0x00,0xcc,0xaf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc af 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecw z0.s, pow2
// CHECK-INST: uqdecw z0.s, pow2
// CHECK-ENCODING: [0x00,0xcc,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 cc a0 04 <unknown>

test/MC/AArch64/SVE/uqincd-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqincd x0, #-1 // CHECK-NEXT: uqincd x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincd x0, #32 uqincd x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqincd x0, #32 // CHECK-NEXT: uqincd x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uqincd z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincd z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqincd z0.d, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincd z0.d, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqincd z0.d, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincd z0.d, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqincd.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f7 f0 04 <unknown> // CHECK-UNKNOWN: 60 f7 f0 04 <unknown>
uqincd x0, #28 uqincd x0, #28
// CHECK-INST: uqincd x0, #28 // CHECK-INST: uqincd x0, #28
// CHECK-ENCODING: [0x80,0xf7,0xf0,0x04] // CHECK-ENCODING: [0x80,0xf7,0xf0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f7 f0 04 <unknown> // CHECK-UNKNOWN: 80 f7 f0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincd z0.d
// CHECK-INST: uqincd z0.d
// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincd z0.d, pow2, mul #16
// CHECK-INST: uqincd z0.d, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc4,0xef,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 ef 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincd z0.d, pow2
// CHECK-INST: uqincd z0.d, pow2
// CHECK-ENCODING: [0x00,0xc4,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 e0 04 <unknown>

test/MC/AArch64/SVE/uqinch-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqinch x0, #-1 // CHECK-NEXT: uqinch x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqinch x0, #32 uqinch x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqinch x0, #32 // CHECK-NEXT: uqinch x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.h, p0/z, z7.h
uqinch z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqinch z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
uqinch z0.h, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqinch z0.h, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
uqinch z0.h, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqinch z0.h, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqinch.s

Show First 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f7 70 04 <unknown> // CHECK-UNKNOWN: 60 f7 70 04 <unknown>
uqinch x0, #28 uqinch x0, #28
// CHECK-INST: uqinch x0, #28 // CHECK-INST: uqinch x0, #28
// CHECK-ENCODING: [0x80,0xf7,0x70,0x04] // CHECK-ENCODING: [0x80,0xf7,0x70,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f7 70 04 <unknown> // CHECK-UNKNOWN: 80 f7 70 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqinch z0.h
// CHECK-INST: uqinch z0.h
// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqinch z0.h, pow2, mul #16
// CHECK-INST: uqinch z0.h, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 6f 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqinch z0.h, pow2
// CHECK-INST: uqinch z0.h, pow2
// CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 60 04 <unknown>

test/MC/AArch64/SVE/uqincp-diagnostics.s

Show All 40 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: uqincp x0, p0/m // CHECK-NEXT: uqincp x0, p0/m
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincp x0, p0.q uqincp x0, p0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: uqincp x0, p0.q // CHECK-NEXT: uqincp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uqincp z0.d, p0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincp z0.d, p0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqincp.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown> // CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.d, p0 uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0 // CHECK-INST: uqincp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25] // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown> // CHECK-UNKNOWN: 00 80 e9 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>

test/MC/AArch64/SVE/uqincw-diagnostics.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqincw x0, #-1 // CHECK-NEXT: uqincw x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincw x0, #32 uqincw x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: uqincw x0, #32 // CHECK-NEXT: uqincw x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
uqincw z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincw z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqincw z0.s, pow2, mul #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincw z0.s, pow2, mul #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqincw z0.s, pow2
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqincw z0.s, pow2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqincw.s

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f7 b0 04 <unknown> // CHECK-UNKNOWN: 60 f7 b0 04 <unknown>
uqincw x0, #28 uqincw x0, #28
// CHECK-INST: uqincw x0, #28 // CHECK-INST: uqincw x0, #28
// CHECK-ENCODING: [0x80,0xf7,0xb0,0x04] // CHECK-ENCODING: [0x80,0xf7,0xb0,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f7 b0 04 <unknown> // CHECK-UNKNOWN: 80 f7 b0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincw z0.s
// CHECK-INST: uqincw z0.s
// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincw z0.s, pow2, mul #16
// CHECK-INST: uqincw z0.s, pow2, mul #16
// CHECK-ENCODING: [0x00,0xc4,0xaf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 af 04 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincw z0.s, pow2
// CHECK-INST: uqincw z0.s, pow2
// CHECK-ENCODING: [0x00,0xc4,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c4 a0 04 <unknown>

test/MC/AArch64/SVE/uqsub-diagnostics.s

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: uqsub z0.d, z0.d, #256, lsl #8 // CHECK-NEXT: uqsub z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqsub z0.d, z0.d, #65536 uqsub z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: uqsub z0.d, z0.d, #65536 // CHECK-NEXT: uqsub z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uqsub z31.d, z31.d, #65280
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uqsub z31.d, z31.d, #65280
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
uqsub z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqsub z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
uqsub z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqsub z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uqsub.s

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e7 25 <unknown> // CHECK-UNKNOWN: ff ff e7 25 <unknown>
uqsub z31.d, z31.d, #65280 uqsub z31.d, z31.d, #65280
// CHECK-INST: uqsub z31.d, z31.d, #65280 // CHECK-INST: uqsub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe7,0x25] // CHECK-ENCODING: [0xff,0xff,0xe7,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e7 25 <unknown> // CHECK-UNKNOWN: ff ff e7 25 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqsub z31.d, z31.d, #65280
// CHECK-INST: uqsub z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe7,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e7 25 <unknown>

test/MC/AArch64/SVE/uunpkhi-diagnostics.s

Show All 12 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uunpkhi z0.s, z0.b // CHECK-NEXT: uunpkhi z0.s, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uunpkhi z0.d, z0.h uunpkhi z0.d, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uunpkhi z0.d, z0.h // CHECK-NEXT: uunpkhi z0.d, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uunpkhi z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uunpkhi z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uunpkhi z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uunpkhi z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uunpklo-diagnostics.s

Show All 12 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uunpklo z0.s, z0.b // CHECK-NEXT: uunpklo z0.s, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uunpklo z0.d, z0.h uunpklo z0.d, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uunpklo z0.d, z0.h // CHECK-NEXT: uunpklo z0.d, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uunpklo z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uunpklo z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uunpklo z31.d, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uunpklo z31.d, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uxtb.s

Show All 36 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 91 04 <unknown> // CHECK-UNKNOWN: ff bf 91 04 <unknown>
uxtb z31.d, p7/m, z31.d uxtb z31.d, p7/m, z31.d
// CHECK-INST: uxtb z31.d, p7/m, z31.d // CHECK-INST: uxtb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd1,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd1,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d1 04 <unknown> // CHECK-UNKNOWN: ff bf d1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
uxtb z4.d, p7/m, z31.d
// CHECK-INST: uxtb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d1 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
uxtb z4.d, p7/m, z31.d
// CHECK-INST: uxtb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d1 04 <unknown>

test/MC/AArch64/SVE/uxth.s

Show All 24 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 93 04 <unknown> // CHECK-UNKNOWN: ff bf 93 04 <unknown>
uxth z31.d, p7/m, z31.d uxth z31.d, p7/m, z31.d
// CHECK-INST: uxth z31.d, p7/m, z31.d // CHECK-INST: uxth z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd3,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d3 04 <unknown> // CHECK-UNKNOWN: ff bf d3 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
uxth z4.d, p7/m, z31.d
// CHECK-INST: uxth z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d3 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
uxth z4.d, p7/m, z31.d
// CHECK-INST: uxth z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d3 04 <unknown>

test/MC/AArch64/SVE/uxtw.s

Show All 12 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d5 04 <unknown> // CHECK-UNKNOWN: 00 a0 d5 04 <unknown>
uxtw z31.d, p7/m, z31.d uxtw z31.d, p7/m, z31.d
// CHECK-INST: uxtw z31.d, p7/m, z31.d // CHECK-INST: uxtw z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd5,0x04] // CHECK-ENCODING: [0xff,0xbf,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d5 04 <unknown> // CHECK-UNKNOWN: ff bf d5 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
uxtw z4.d, p7/m, z31.d
// CHECK-INST: uxtw z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d5 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
uxtw z4.d, p7/m, z31.d
// CHECK-INST: uxtw z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e4 bf d5 04 <unknown>

test/MC/AArch64/SVE/uzp1-diagnostics.s

Show All 35 Lines
// CHECK-NEXT: uzp1 z1.s, z2.s, p3.s // CHECK-NEXT: uzp1 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
uzp1 p1.s, p2.s, z3.s uzp1 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uzp1 p1.s, p2.s, z3.s // CHECK-NEXT: uzp1 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uzp1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uzp1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/uzp2-diagnostics.s

Show All 35 Lines
// CHECK-NEXT: uzp2 z1.s, z2.s, p3.s // CHECK-NEXT: uzp2 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
uzp2 p1.s, p2.s, z3.s uzp2 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uzp2 p1.s, p2.s, z3.s // CHECK-NEXT: uzp2 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uzp2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uzp2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/zip1-diagnostics.s

Show All 35 Lines
// CHECK-NEXT: zip1 z1.s, z2.s, p3.s // CHECK-NEXT: zip1 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
zip1 p1.s, p2.s, z3.s zip1 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip1 p1.s, p2.s, z3.s // CHECK-NEXT: zip1 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
zip1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: zip1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
zip1 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: zip1 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/zip2-diagnostics.s

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// CHECK-NEXT: zip2 z1.s, z2.s, p3.s // CHECK-NEXT: zip2 z1.s, z2.s, p3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Combining predicate and data registers as operands // Combining predicate and data registers as operands
zip2 p1.s, p2.s, z3.s zip2 p1.s, p2.s, z3.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zip2 p1.s, p2.s, z3.s // CHECK-NEXT: zip2 p1.s, p2.s, z3.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
zip2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: zip2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
zip2 z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: zip2 z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: