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Differential D48869

[AArch64][SVE] Asm: Support for SVE condition code aliases
ClosedPublic

Authored by sdesmalen on Jul 3 2018, 2:35 AM.

Details

Reviewers
rengolin
fhahn
SjoerdMeijer
samparker
javed.absar
Commits
rGe31e6d46dd63: [AArch64][SVE] Asm: Support for SVE condition code aliases
rL336245: [AArch64][SVE] Asm: Support for SVE condition code aliases
Summary

SVE overloads the AArch64 PSTATE condition flags and introduces
a set of condition code aliases for the assembler. The
details are described in section 2.2 of the architecture
reference manual supplement for SVE.

In short:

SVE alias =>  AArch64 name
--------------------------
NONE      => EQ
ANY       => NE
NLAST     => HS
LAST      => LO
FIRST     => MI
NFRST     => PL
PMORE     => HI
PLAST     => LS
TCONT     => GE
TSTOP     => LT

Diff Detail

Event Timeline

sdesmalen created this revision.Jul 3 2018, 2:35 AM
Herald added a reviewer: javed.absar. · View Herald TranscriptJul 3 2018, 2:35 AM
Herald added subscribers: rkruppe, kristof.beyls, tschuett. · View Herald Transcript
sdesmalen added inline comments.Jul 3 2018, 2:38 AM
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
2506

I just realise there is an unnecessary whitespace change here that someone will surely comment on :) I'll remove that before committing.

fhahn accepted this revision.Jul 3 2018, 4:18 AM

LGTM, thanks

This revision is now accepted and ready to land.Jul 3 2018, 4:18 AM
Closed by commit rL336245: [AArch64][SVE] Asm: Support for SVE condition code aliases (authored by s.desmalen). · Explain WhyJul 4 2018, 1:55 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
AsmParser/
52 lines
test/
MC/
AArch64/
SVE/
66 lines

Diff 153884

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 2,497 Lines • ▼ Show 20 LinesAArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount,
S, E, getContext())); S, E, getContext()));
return MatchOperand_Success; return MatchOperand_Success;
} }
/// parseCondCodeString - Parse a Condition Code string. /// parseCondCodeString - Parse a Condition Code string.
AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) { AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) {
AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
.Case("eq", AArch64CC::EQ) .Case("eq", AArch64CC::EQ)
sdesmalenAuthorUnsubmitted
Not Done
ReplyInline Actions

I just realise there is an unnecessary whitespace change here that someone will surely comment on :) I'll remove that before committing.

sdesmalen: I just realise there is an unnecessary whitespace change here that someone will surely comment…
.Case("ne", AArch64CC::NE) .Case("ne", AArch64CC::NE)
.Case("cs", AArch64CC::HS) .Case("cs", AArch64CC::HS)
.Case("hs", AArch64CC::HS) .Case("hs", AArch64CC::HS)
.Case("cc", AArch64CC::LO) .Case("cc", AArch64CC::LO)
.Case("lo", AArch64CC::LO) .Case("lo", AArch64CC::LO)
.Case("mi", AArch64CC::MI) .Case("mi", AArch64CC::MI)
.Case("pl", AArch64CC::PL) .Case("pl", AArch64CC::PL)
.Case("vs", AArch64CC::VS) .Case("vs", AArch64CC::VS)
.Case("vc", AArch64CC::VC) .Case("vc", AArch64CC::VC)
.Case("hi", AArch64CC::HI) .Case("hi", AArch64CC::HI)
.Case("ls", AArch64CC::LS) .Case("ls", AArch64CC::LS)
.Case("ge", AArch64CC::GE) .Case("ge", AArch64CC::GE)
.Case("lt", AArch64CC::LT) .Case("lt", AArch64CC::LT)
.Case("gt", AArch64CC::GT) .Case("gt", AArch64CC::GT)
.Case("le", AArch64CC::LE) .Case("le", AArch64CC::LE)
.Case("al", AArch64CC::AL) .Case("al", AArch64CC::AL)
.Case("nv", AArch64CC::NV) .Case("nv", AArch64CC::NV)
.Default(AArch64CC::Invalid); .Default(AArch64CC::Invalid);
if (CC == AArch64CC::Invalid &&
getSTI().getFeatureBits()[AArch64::FeatureSVE])
CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
.Case("none", AArch64CC::EQ)
.Case("any", AArch64CC::NE)
.Case("nlast", AArch64CC::HS)
.Case("last", AArch64CC::LO)
.Case("first", AArch64CC::MI)
.Case("nfrst", AArch64CC::PL)
.Case("pmore", AArch64CC::HI)
.Case("plast", AArch64CC::LS)
.Case("tcont", AArch64CC::GE)
.Case("tstop", AArch64CC::LT)
.Default(AArch64CC::Invalid);
return CC; return CC;
} }
/// parseCondCode - Parse a Condition Code operand. /// parseCondCode - Parse a Condition Code operand.
bool AArch64AsmParser::parseCondCode(OperandVector &Operands, bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
bool invertCondCode) { bool invertCondCode) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
SMLoc S = getLoc(); SMLoc S = getLoc();
▲ Show 20 Lines • Show All 2,772 Lines • Show Last 20 Lines

test/MC/AArch64/SVE/condtion-codes.s

  • This file was added.
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+sve < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-sve < %s 2>&1 | FileCheck %s --check-prefix=CHECK-DIAG
//------------------------------------------------------------------------------
// Condition code aliases for SVE
//------------------------------------------------------------------------------
b.none lbl
// CHECK: b.eq lbl // encoding: [0bAAA00000,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.none lbl
b.any lbl
// CHECK: b.ne lbl // encoding: [0bAAA00001,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.any lbl
b.nlast lbl
// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.nlast lbl
b.last lbl
// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.last lbl
b.first lbl
// CHECK: b.mi lbl // encoding: [0bAAA00100,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.first lbl
b.nfrst lbl
// CHECK: b.pl lbl // encoding: [0bAAA00101,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.nfrst lbl
b.pmore lbl
// CHECK: b.hi lbl // encoding: [0bAAA01000,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.pmore lbl
b.plast lbl
// CHECK: b.ls lbl // encoding: [0bAAA01001,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.plast lbl
b.tcont lbl
// CHECK: b.ge lbl // encoding: [0bAAA01010,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.tcont lbl
b.tstop lbl
// CHECK: b.lt lbl // encoding: [0bAAA01011,A,A,0x54]
// CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// CHECK-DIAG: invalid condition code
// CHECK-DIAG-NEXT: b.tstop lbl