[AArch64][SVE] Asm: Support for SVE condition code aliases

[sdesmalen]

Summary

SVE overloads the AArch64 PSTATE condition flags and introduces
a set of condition code aliases for the assembler. The
details are described in section 2.2 of the architecture
reference manual supplement for SVE.

In short:

SVE alias =>  AArch64 name
--------------------------
NONE      => EQ
ANY       => NE
NLAST     => HS
LAST      => LO
FIRST     => MI
NFRST     => PL
PMORE     => HI
PLAST     => LS
TCONT     => GE
TSTOP     => LT

[sdesmalen]

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

2506 ↗

(On Diff #153884)

I just realise there is an unnecessary whitespace change here that someone will surely comment on :) I'll remove that before committing.

[fhahn]

LGTM, thanks

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
                     .Case("ls", AArch64CC::LS)
                     .Case("ge", AArch64CC::GE)
                     .Case("lt", AArch64CC::LT)
                     .Case("gt", AArch64CC::GT)
                     .Case("le", AArch64CC::LE)
                     .Case("al", AArch64CC::AL)
                     .Case("nv", AArch64CC::NV)
                     .Default(AArch64CC::Invalid);
+
+  if (CC == AArch64CC::Invalid &&
+      getSTI().getFeatureBits()[AArch64::FeatureSVE])
+    CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
+                    .Case("none",  AArch64CC::EQ)
+                    .Case("any",   AArch64CC::NE)
+                    .Case("nlast", AArch64CC::HS)
+                    .Case("last",  AArch64CC::LO)
+                    .Case("first", AArch64CC::MI)
+                    .Case("nfrst", AArch64CC::PL)
+                    .Case("pmore", AArch64CC::HI)
+                    .Case("plast", AArch64CC::LS)
+                    .Case("tcont", AArch64CC::GE)
+                    .Case("tstop", AArch64CC::LT)
+                    .Default(AArch64CC::Invalid);
+
   return CC;
 }
 
 /// parseCondCode - Parse a Condition Code operand.
 bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
                                      bool invertCondCode) {
   MCAsmParser &Parser = getParser();
   SMLoc S = getLoc();

llvm/trunk/test/MC/AArch64/SVE/condtion-codes.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+sve < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-sve < %s 2>&1 | FileCheck %s --check-prefix=CHECK-DIAG
+
+//------------------------------------------------------------------------------
+// Condition code aliases for SVE
+//------------------------------------------------------------------------------
+
+        b.none lbl
+// CHECK: b.eq lbl     // encoding: [0bAAA00000,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.none lbl
+
+        b.any lbl
+// CHECK: b.ne lbl     // encoding: [0bAAA00001,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.any lbl
+
+        b.nlast lbl
+// CHECK: b.hs lbl     // encoding: [0bAAA00010,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.nlast lbl
+
+        b.last lbl
+// CHECK: b.lo lbl     // encoding: [0bAAA00011,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.last lbl
+
+        b.first lbl
+// CHECK: b.mi lbl     // encoding: [0bAAA00100,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.first lbl
+
+        b.nfrst lbl
+// CHECK: b.pl lbl     // encoding: [0bAAA00101,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.nfrst lbl
+
+        b.pmore lbl
+// CHECK: b.hi lbl     // encoding: [0bAAA01000,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.pmore lbl
+
+        b.plast lbl
+// CHECK: b.ls lbl     // encoding: [0bAAA01001,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.plast lbl
+
+        b.tcont lbl
+// CHECK: b.ge lbl     // encoding: [0bAAA01010,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.tcont lbl
+
+        b.tstop lbl
+// CHECK: b.lt lbl     // encoding: [0bAAA01011,A,A,0x54]
+// CHECK-NEXT:         //   fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK-DIAG:  invalid condition code
+// CHECK-DIAG-NEXT:  b.tstop lbl