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[AArch64][SVE] Asm: Support for FMUL (indexed)
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Authored by sdesmalen on Jul 2 2018, 2:51 AM.

Details

Summary

Unpredicated FP-multiply of SVE vector with a vector-element given by
vector[index], for example:

fmul z0.s, z1.s, z2.s[0]

which performs an unpredicated FP-multiply of all 32-bit elements in
'z1' with the first element from 'z2'.

This patch adds restricted register classes for SVE vectors:

ZPR_3b (only z0..z7 are allowed)  - for indexed vector of 16/32-bit elements.
ZPR_4b (only z0..z15 are allowed) - for indexed vector of 64-bit elements.

Diff Detail

Repository
rL LLVM

Event Timeline

sdesmalen created this revision.Jul 2 2018, 2:51 AM
fhahn accepted this revision.Jul 3 2018, 4:11 AM

LGTM, thanks!

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
509 ↗(On Diff #153688)

nit: misaligned

517 ↗(On Diff #153688)

nit: misaligned

This revision is now accepted and ready to land.Jul 3 2018, 4:11 AM
sdesmalen marked 2 inline comments as done.Jul 3 2018, 8:35 AM
This revision was automatically updated to reflect the committed changes.