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[VPlan] Introduce condition bit in VPBlockBase.
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Authored by dcaballe on Jul 1 2018, 10:14 PM.

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Summary

Context: Patch Series #1 for outer loop vectorization support in LV
using VPlan. (RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).

This patch introduces a VPValue in VPBlockBase to represent the condition
bit that is used as successor selector when a block has multiple successors.
This information wasn't necessary until now, when we are about to introduce
outer loop vectorization support in VPlan code gen.

Representing the condition bit as a field in VPBlockBase fits well with the VPlan recipe-based
code currently used in the inner loop vectorizer path and its decision about not representing
branches at VPlan instruction level. It also aligns well with our current internal implementation,
which will allow us to upstream patches quicker. However, we think that the explicit representation
of branches at VPlan instruction level will better fit with the VPInstruction model and its DU graph.
For that reason, we are planning to change the proposed condition bit representation (and lack of
branches) in the short term, so this patch should be seen as a stepping stone towards that direction.

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Repository
rL LLVM

Event Timeline

dcaballe created this revision.Jul 1 2018, 10:14 PM
fhahn accepted this revision.Jul 6 2018, 2:35 AM

LGTM, thanks.

This revision is now accepted and ready to land.Jul 6 2018, 2:35 AM

Thanks, Florian! I'll commit next week.

Diego.

This revision was automatically updated to reflect the committed changes.