[GISel]: Add opcode to translate addrspacecast

[aditya_nandakumar]

Summary

Added Opcode G_ADDR_SPACE_CAST for translation.

[volkan]

LGTM.

[aditya_nandakumar]

committed in r335388

include/llvm/CodeGen/GlobalISel/IRTranslator.h

private:
   }
   bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder) {
     return false;
   }
   bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder) {
     return false;
   }
   bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
-    return false;
+    return translateCast(TargetOpcode::G_ADDR_SPACE_CAST, U, MIRBuilder);
   }
   bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
     return false;
   }
   bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
     return false;
   }
   bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {

include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
 
 /// Generic shufflevector.
 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
 
 /// Generic byte swap.
 HANDLE_TARGET_OPCODE(G_BSWAP)
 
+/// Generic AddressSpaceCast.
+HANDLE_TARGET_OPCODE(G_ADDR_SPACE_CAST)
+
 // TODO: Add more generic opcodes as we move along.
 
 /// Marker for the end of the generic opcode.
 /// This is used to check if an opcode is in the range of the
 /// generic opcodes.
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BSWAP)
 
 /// BUILTIN_OP_END - This must be the last enum value in this list.
 /// The target-specific post-isel opcode values start here.
 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)

include/llvm/Target/GenericOpcodes.td

 }
 
 def G_BSWAP : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
   let hasSideEffects = 0;
 }
 
+def G_ADDR_SPACE_CAST : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src);
+  let hasSideEffects = 0;
+}
 //------------------------------------------------------------------------------
 // Binary ops.
 //------------------------------------------------------------------------------
 
 // Generic addition.
 def G_ADD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK: $x0 = COPY [[RES2]]
 ; CHECK: RET_ReallyLR implicit $x0
 define i64 @bitcast(i64 %a) {
   %res1 = bitcast i64 %a to <2 x i32>
   %res2 = bitcast <2 x i32> %res1 to i64
   ret i64 %res2
 }
 
+; CHECK-LABEL: name: addrspacecast
+; CHECK: [[ARG1:%[0-9]+]]:_(p1) = COPY $x0
+; CHECK: [[RES1:%[0-9]+]]:_(p2) = G_ADDR_SPACE_CAST [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(p0) = G_ADDR_SPACE_CAST [[RES1]]
+; CHECK: $x0 = COPY [[RES2]]
+; CHECK: RET_ReallyLR implicit $x0
+define i64* @addrspacecast(i32 addrspace(1)* %a) {
+  %res1 = addrspacecast i32 addrspace(1)* %a to i64 addrspace(2)*
+  %res2 = addrspacecast i64 addrspace(2)* %res1 to i64*
+  ret i64* %res2
+}
+
 ; CHECK-LABEL: name: trunc
 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
 ; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
 ; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
 define void @trunc(i64 %a) {
   %vecptr = alloca <4 x i32>
   %vec = load <4 x i32>, <4 x i32>* %vecptr