[Power9] [LLVM] Add __float128 exponent GET and SET builtins

[stefanp]

Summary

Added

__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp

Builtins should behave the same way as in GCC.

[lei]

lib/Target/PowerPC/PPCInstrVSX.td

2686

indent by 2 here.

test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

103

register?

[nemanjai]

Can you put a link in the description of the patch as to where the GCC builtins are documented (if such a document exists). The naming seems inconsistent and I don't see it at https://gcc.gnu.org/onlinedocs/gcc-8.1.0/gcc/PowerPC-Built-in-Functions.html.

[stefanp]

I looked into the naming of those builtins.
GCC does document the overloaded versions of those functions:
scalar_extract_exp for __builtin_vsx_scalar_extract_expq
scalar_insert_exp for __builtin_vsx_scalar_insert_exp_qp

We could add wrappers to these builtins the way that they do or we could (at least for now) just put in the __builtin versions.

[nemanjai]

test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

103

Not only that, but we should check that the sequence with the register move is part of the emitted sequence (both tests).

[stefanp]

Update patch based on reviewer comments.

[nemanjai]

LGTM.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_mulf128_round_to_odd
       : GCCBuiltin<"__builtin_mulf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_divf128_round_to_odd
       : GCCBuiltin<"__builtin_divf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_fmaf128_round_to_odd
       : GCCBuiltin<"__builtin_fmaf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
+  def int_ppc_scalar_extract_expq
+      : GCCBuiltin<"__builtin_vsx_scalar_extract_expq">,
+        Intrinsic <[llvm_i64_ty], [llvm_f128_ty], [IntrNoMem]>;
+  def int_ppc_scalar_insert_exp_qp
+      : GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
+        Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
 
 }
 
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
   class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
                               list<LLVMType> param_types,

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
   def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
                           "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>, UseVSXReg;
   // vB NOTE: only vB.dword[0] is used, that's why we don't use
   //          X_VT5_VA5_VB5 form
   def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
                           "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
 
+  def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)),
+            (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>;
+
   // Extract Exponent/Significand DP/QP
   def XSXEXPDP : XX2_RT5_XO5_XB6<60,  0, 347, "xsxexpdp", []>;
   def XSXSIGDP : XX2_RT5_XO5_XB6<60,  1, 347, "xsxsigdp", []>;
 
   def XSXEXPQP : X_VT5_XO5_VB5  <63,  2, 804, "xsxexpqp", []>;
   def XSXSIGQP : X_VT5_XO5_VB5  <63, 18, 804, "xsxsigqp", []>;
 
+  def : Pat<(i64 (int_ppc_scalar_extract_expq  f128:$vA)),
+            (i64 (MFVSRD (EXTRACT_SUBREG
+                           (v2i64 (XSXEXPQP $vA)), sub_64)))>;
+
   // Vector Insert Word
   let UseVSXReg = 1 in {
   // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
   def XXINSERTW   :
     XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
                      (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM),
                      "xxinsertw $XT, $XB, $UIM", IIC_VecFP,
                      [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,

test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

entry:
   %0 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %a)
   ret double %0
 ; CHECK-LABEL: testTruncOdd
 ; CHECK: xscvqpdpo v2, v2
 ; CHECK: xscpsgndp f1, v2, v2
 ; CHECK: blr
 }
 
 declare double @llvm.ppc.truncf128.round.to.odd(fp128)
+
+; Function Attrs: noinline nounwind optnone
+define fp128 @insert_exp_qp(i64 %b) {
+entry:
+  %b.addr = alloca i64, align 8
+  store i64 %b, i64* %b.addr, align 8
+  %0 = load fp128, fp128* @A, align 16
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
+  ret fp128 %2
+; CHECK-LABEL: insert_exp_qp
+; CHECK: mtvsrd [[FPREG:f[0-9]+]], r3
+; CHECK: lxvx [[VECREG:v[0-9]+]]
+; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
+
+; Function Attrs: noinline nounwind optnone
+define i64 @extract_exp() {
+entry:
+  %0 = load fp128, fp128* @A, align 16
+  %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0)
+  ret i64 %1
+; CHECK-LABEL: extract_exp
+; CHECK: lxvx [[VECIN:v[0-9]+]]
+; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]]
+; CHECK: mfvsrd r3, [[VECOUT]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.scalar.extract.expq(fp128)
+