[PowerPC] The __float128 type should only be available on Power9

[stefanp]

Summary

Hardware support for IEEE __float128 was introduced in power 9.
We will now produce an error for the option -mfloat128 when run on any power PC older than power 9.

lib/Basic/Targets/PPC.h

 
 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
 
 #include "OSTargets.h"
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/Compiler.h"
 
 namespace clang {
 namespace targets {
 
 // PPC abstract base class
 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
+
+  /// Flags for architecture specific defines.
+  typedef enum {
+    ArchDefineNone = 0,
+    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
+    ArchDefinePpcgr = 1 << 1,
+    ArchDefinePpcsq = 1 << 2,
+    ArchDefine440 = 1 << 3,
+    ArchDefine603 = 1 << 4,
+    ArchDefine604 = 1 << 5,
+    ArchDefinePwr4 = 1 << 6,
+    ArchDefinePwr5 = 1 << 7,
+    ArchDefinePwr5x = 1 << 8,
+    ArchDefinePwr6 = 1 << 9,
+    ArchDefinePwr6x = 1 << 10,
+    ArchDefinePwr7 = 1 << 11,
+    ArchDefinePwr8 = 1 << 12,
+    ArchDefinePwr9 = 1 << 13,
+    ArchDefineA2 = 1 << 14,
+    ArchDefineA2q = 1 << 15
+  } ArchDefineTypes;
+
+
+  ArchDefineTypes ArchDefs;
   static const Builtin::Info BuiltinInfo[];
   static const char *const GCCRegNames[];
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   std::string CPU;
 
   // Target cpu features.
   bool HasAltivec;
   bool HasVSX;

 protected:
   std::string ABI;
 
 public:
   PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple), HasAltivec(false), HasVSX(false),
         HasP8Vector(false), HasP8Crypto(false), HasDirectMove(false),
         HasQPX(false), HasHTM(false), HasBPERMD(false), HasExtDiv(false),
-        HasP9Vector(false) {
+        HasP9Vector(false), ArchDefs(ArchDefineNone) {
     SuitableAlign = 128;
     SimdDefaultAlign = 128;
     LongDoubleWidth = LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
   }
 
-  /// Flags for architecture specific defines.
-  typedef enum {
-    ArchDefineNone = 0,
-    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
-    ArchDefinePpcgr = 1 << 1,
-    ArchDefinePpcsq = 1 << 2,
-    ArchDefine440 = 1 << 3,
-    ArchDefine603 = 1 << 4,
-    ArchDefine604 = 1 << 5,
-    ArchDefinePwr4 = 1 << 6,
-    ArchDefinePwr5 = 1 << 7,
-    ArchDefinePwr5x = 1 << 8,
-    ArchDefinePwr6 = 1 << 9,
-    ArchDefinePwr6x = 1 << 10,
-    ArchDefinePwr7 = 1 << 11,
-    ArchDefinePwr8 = 1 << 12,
-    ArchDefinePwr9 = 1 << 13,
-    ArchDefineA2 = 1 << 14,
-    ArchDefineA2q = 1 << 15
-  } ArchDefineTypes;
-
   // Set the language option for altivec based on our value.
   void adjust(LangOptions &Opts) override;
 
   // Note: GCC recognizes the following additional cpus:
   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
   //  titan, rs64.
   bool isValidCPUName(StringRef Name) const override;
   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
 
   bool setCPU(const std::string &Name) override {
     bool CPUKnown = isValidCPUName(Name);
-    if (CPUKnown)
+    if (CPUKnown) {
       CPU = Name;
+
+      // CPU identification.
+      ArchDefs =
+          (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
+              .Case("440", ArchDefineName)
+              .Case("450", ArchDefineName | ArchDefine440)
+              .Case("601", ArchDefineName)
+              .Case("602", ArchDefineName | ArchDefinePpcgr)
+              .Case("603", ArchDefineName | ArchDefinePpcgr)
+              .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
+              .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
+              .Case("604", ArchDefineName | ArchDefinePpcgr)
+              .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
+              .Case("620", ArchDefineName | ArchDefinePpcgr)
+              .Case("630", ArchDefineName | ArchDefinePpcgr)
+              .Case("7400", ArchDefineName | ArchDefinePpcgr)
+              .Case("7450", ArchDefineName | ArchDefinePpcgr)
+              .Case("750", ArchDefineName | ArchDefinePpcgr)
+              .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
+                               ArchDefinePpcsq)
+              .Case("a2", ArchDefineA2)
+              .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
+              .Cases("power3", "pwr3", ArchDefinePpcgr)
+              .Cases("power4", "pwr4",
+                    ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+              .Cases("power5", "pwr5",
+                    ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+                        ArchDefinePpcsq)
+              .Cases("power5x", "pwr5x",
+                    ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
+                        ArchDefinePpcgr | ArchDefinePpcsq)
+              .Cases("power6", "pwr6",
+                    ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
+                        ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+              .Cases("power6x", "pwr6x",
+                    ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
+                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+                        ArchDefinePpcsq)
+              .Cases("power7", "pwr7",
+                    ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
+                        ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
+                        ArchDefinePpcgr | ArchDefinePpcsq)
+              // powerpc64le automatically defaults to at least power8.
+              .Cases("power8", "pwr8", "ppc64le",
+                    ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
+                        ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
+                        ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+              .Cases("power9", "pwr9",
+                    ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
+                        ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
+                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+                        ArchDefinePpcsq)
+              .Default(ArchDefineNone);
+    }
     return CPUKnown;
   }
 
   StringRef getABI() const override { return ABI; }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   bool isCLZForZeroUndef() const override { return false; }

lib/Basic/Targets/PPC.cpp

 // This file implements PPC TargetInfo objects.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/MacroBuilder.h"
 #include "clang/Basic/TargetBuiltins.h"
-#include "llvm/ADT/StringSwitch.h"
 
 using namespace clang;
 using namespace clang::targets;
 
 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
if (LongDoubleWidth == 128) {
     Builder.defineMacro("__LONGDOUBLE128");
   }
 
   // Define this for elfv2 (64-bit only) or 64-bit darwin.
   if (ABI == "elfv2" ||
       (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
     Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
 
-  // CPU identification.
-  ArchDefineTypes defs =
-      (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
-          .Case("440", ArchDefineName)
-          .Case("450", ArchDefineName | ArchDefine440)
-          .Case("601", ArchDefineName)
-          .Case("602", ArchDefineName | ArchDefinePpcgr)
-          .Case("603", ArchDefineName | ArchDefinePpcgr)
-          .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
-          .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
-          .Case("604", ArchDefineName | ArchDefinePpcgr)
-          .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
-          .Case("620", ArchDefineName | ArchDefinePpcgr)
-          .Case("630", ArchDefineName | ArchDefinePpcgr)
-          .Case("7400", ArchDefineName | ArchDefinePpcgr)
-          .Case("7450", ArchDefineName | ArchDefinePpcgr)
-          .Case("750", ArchDefineName | ArchDefinePpcgr)
-          .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
-                           ArchDefinePpcsq)
-          .Case("a2", ArchDefineA2)
-          .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
-          .Case("pwr3", ArchDefinePpcgr)
-          .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
-                            ArchDefinePpcsq)
-          .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
-                             ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
-                            ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
-                             ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
-                             ArchDefinePpcsq)
-          .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
-                            ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
-                            ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
-                            ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
-                            ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
-                            ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
-                            ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
-                            ArchDefinePpcsq)
-          .Case("power3", ArchDefinePpcgr)
-          .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
-                              ArchDefinePpcsq)
-          .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
-                               ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
-                              ArchDefinePwr4 | ArchDefinePpcgr |
-                              ArchDefinePpcsq)
-          .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
-                               ArchDefinePwr5 | ArchDefinePwr4 |
-                               ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
-                              ArchDefinePwr5x | ArchDefinePwr5 |
-                              ArchDefinePwr4 | ArchDefinePpcgr |
-                              ArchDefinePpcsq)
-          .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
-                              ArchDefinePwr6 | ArchDefinePwr5x |
-                              ArchDefinePwr5 | ArchDefinePwr4 |
-                              ArchDefinePpcgr | ArchDefinePpcsq)
-          .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
-                              ArchDefinePwr6x | ArchDefinePwr6 |
-                              ArchDefinePwr5x | ArchDefinePwr5 |
-                              ArchDefinePwr4 | ArchDefinePpcgr |
-                              ArchDefinePpcsq)
-          // powerpc64le automatically defaults to at least power8.
-          .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
-                               ArchDefinePwr6 | ArchDefinePwr5x |
-                               ArchDefinePwr5 | ArchDefinePwr4 |
-                               ArchDefinePpcgr | ArchDefinePpcsq)
-          .Default(ArchDefineNone);
-
-  if (defs & ArchDefineName)
+  if (ArchDefs & ArchDefineName)
     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
-  if (defs & ArchDefinePpcgr)
+  if (ArchDefs & ArchDefinePpcgr)
     Builder.defineMacro("_ARCH_PPCGR");
-  if (defs & ArchDefinePpcsq)
+  if (ArchDefs & ArchDefinePpcsq)
     Builder.defineMacro("_ARCH_PPCSQ");
-  if (defs & ArchDefine440)
+  if (ArchDefs & ArchDefine440)
     Builder.defineMacro("_ARCH_440");
-  if (defs & ArchDefine603)
+  if (ArchDefs & ArchDefine603)
     Builder.defineMacro("_ARCH_603");
-  if (defs & ArchDefine604)
+  if (ArchDefs & ArchDefine604)
     Builder.defineMacro("_ARCH_604");
-  if (defs & ArchDefinePwr4)
+  if (ArchDefs & ArchDefinePwr4)
     Builder.defineMacro("_ARCH_PWR4");
-  if (defs & ArchDefinePwr5)
+  if (ArchDefs & ArchDefinePwr5)
     Builder.defineMacro("_ARCH_PWR5");
-  if (defs & ArchDefinePwr5x)
+  if (ArchDefs & ArchDefinePwr5x)
     Builder.defineMacro("_ARCH_PWR5X");
-  if (defs & ArchDefinePwr6)
+  if (ArchDefs & ArchDefinePwr6)
     Builder.defineMacro("_ARCH_PWR6");
-  if (defs & ArchDefinePwr6x)
+  if (ArchDefs & ArchDefinePwr6x)
     Builder.defineMacro("_ARCH_PWR6X");
-  if (defs & ArchDefinePwr7)
+  if (ArchDefs & ArchDefinePwr7)
     Builder.defineMacro("_ARCH_PWR7");
-  if (defs & ArchDefinePwr8)
+  if (ArchDefs & ArchDefinePwr8)
     Builder.defineMacro("_ARCH_PWR8");
-  if (defs & ArchDefinePwr9)
+  if (ArchDefs & ArchDefinePwr9)
     Builder.defineMacro("_ARCH_PWR9");
-  if (defs & ArchDefineA2)
+  if (ArchDefs & ArchDefineA2)
     Builder.defineMacro("_ARCH_A2");
-  if (defs & ArchDefineA2q) {
+  if (ArchDefs & ArchDefineA2q) {
     Builder.defineMacro("_ARCH_A2Q");
     Builder.defineMacro("_ARCH_QP");
   }
 
   if (getTriple().getVendor() == llvm::Triple::BGQ) {
     Builder.defineMacro("__bg__");
     Builder.defineMacro("__THW_BLUEGENE__");
     Builder.defineMacro("__bgq__");
Features["htm"] = llvm::StringSwitch<bool>(CPU)
                         .Case("ppc64le", true)
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Default(false);
 
   if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
     return false;
 
+  if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
+      std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
+          FeaturesVec.end()) {
+    // We have __float128 on PPC but not power 9 and above.
+    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
+    return false;
+  }
+
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("powerpc", true)
       .Case("altivec", HasAltivec)
       .Case("vsx", HasVSX)

test/Driver/ppc-f128-support-check.c

+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=HASF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=power9 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=HASF128
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mfloat128 %s 2>&1 | FileCheck %s --check-prefix=NOF128
+
+#ifdef __FLOAT128__
+static_assert(false, "__float128 enabled");
+#endif
+
+// HASF128: __float128 enabled
+// HASF128-NOT: option '-mfloat128' cannot be specified with
+// NOF128: option '-mfloat128' cannot be specified with
+

test/Preprocessor/init.c

 // PPCPOWER9:#define _ARCH_PWR4 1
 // PPCPOWER9:#define _ARCH_PWR5 1
 // PPCPOWER9:#define _ARCH_PWR5X 1
 // PPCPOWER9:#define _ARCH_PWR6 1
 // PPCPOWER9:#define _ARCH_PWR6X 1
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 //
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power8 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-unknown-linux-gnu -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC64-LINUX %s
 //
 // PPC64-LINUX:#define _ARCH_PPC 1
 // PPC64-LINUX:#define _ARCH_PPC64 1
 // PPC64-LINUX:#define _BIG_ENDIAN 1
 // PPC64-LINUX:#define _CALL_LINUX 1

test/Sema/float128-ld-incompatibility.cpp

 // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
-// RUN: -triple powerpc64le-unknown-linux-gnu -target-cpu pwr8 \
+// RUN: -triple powerpc64le-unknown-linux-gnu -target-cpu pwr9 \
 // RUN: -target-feature +float128 %s
 // RUN: %clang_cc1 -fsyntax-only -std=c++11 -triple x86_64-unknown-linux-gnu -Wno-unused-value -Wno-parentheses %s
 
 __float128 qf();
 long double ldf();
 
 #ifdef __PPC__
 // FIXME: once operations between long double and __float128 are implemented for