[AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
 
   defm ADD_ZI   : sve_int_arith_imm0<0b000, "add">;
   defm SUB_ZI   : sve_int_arith_imm0<0b001, "sub">;
 
   defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
   defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
   defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
 
+  defm FADD_ZPmI    : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
+  defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
+  defm FMAX_ZPmI    : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
+
   // Splat immediate (unpredicated)
   defm DUP_ZI   : sve_int_dup_imm<"dup">;
   defm FDUP_ZI  : sve_int_dup_fpimm<"fdup">;
   defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">;
 
   // Splat immediate (predicated)
   defm CPY_ZPmI  : sve_int_dup_imm_pred_merge<"cpy">;
   defm CPY_ZPzI  : sve_int_dup_imm_pred_zero<"cpy">;

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

#include "AArch64GenAsmMatcher.inc"
   OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
   OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
   template <bool IsSVEPrefetch = false>
   OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
   OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
   OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
   OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
   OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
-  LLVM_ATTRIBUTE_UNUSED
   OperandMatchResultTy tryParseExactFPImm(OperandVector &Operands);
   OperandMatchResultTy tryParseImmWithOptionalShift(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
   bool tryParseNeonVectorRegister(OperandVector &Operands);
   OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
   OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
   template <bool ParseShiftExtend>
   OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidSVEPredicateDReg:
     return Error(Loc, "invalid predicate register.");
   case Match_InvalidSVEPredicate3bAnyReg:
   case Match_InvalidSVEPredicate3bBReg:
   case Match_InvalidSVEPredicate3bHReg:
   case Match_InvalidSVEPredicate3bSReg:
   case Match_InvalidSVEPredicate3bDReg:
     return Error(Loc, "restricted predicate has range [0, 7].");
+  case Match_InvalidSVEExactFPImmOperandHalfOne:
+    return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
+  case Match_InvalidSVEExactFPImmOperandHalfTwo:
+    return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0.");
+  case Match_InvalidSVEExactFPImmOperandZeroOne:
+    return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0.");
   default:
     llvm_unreachable("unexpected error code!");
   }
 }
 
 static const char *getSubtargetFeatureName(uint64_t Val);
 
 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
   case Match_InvalidSVEPredicate3bAnyReg:
   case Match_InvalidSVEPredicate3bBReg:
   case Match_InvalidSVEPredicate3bHReg:
   case Match_InvalidSVEPredicate3bSReg:
   case Match_InvalidSVEPredicate3bDReg:
+  case Match_InvalidSVEExactFPImmOperandHalfOne:
+  case Match_InvalidSVEExactFPImmOperandHalfTwo:
+  case Match_InvalidSVEExactFPImmOperandZeroOne:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
       return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.
     SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc())

lib/Target/AArch64/SVEInstrFormats.td

class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
   let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">";
 }
 
 class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> {
   let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">";
   let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>;
 }
 
+def sve_fpimm_half_one
+    : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half",
+                           "AArch64ExactFPImm::one">;
+def sve_fpimm_half_two
+    : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half",
+                           "AArch64ExactFPImm::two">;
+def sve_fpimm_zero_one
+    : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero",
+                           "AArch64ExactFPImm::one">;
+
 //===----------------------------------------------------------------------===//
 // SVE PTrue - These are used extensively throughout the pattern matching so
 //             it's important we define them first.
 //===----------------------------------------------------------------------===//
 
 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
 : I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
   asm, "\t$Pd, $pattern",

 multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
   def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
   def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
   def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
   def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
 }
 
 //===----------------------------------------------------------------------===//
+// SVE Floating Point Arithmetic - Predicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
+                         ZPRRegOp zprty,
+                         Operand imm_ty>
+: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
+  asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Zdn;
+  bit i1;
+  let Inst{31-24} = 0b01100101;
+  let Inst{23-22} = sz;
+  let Inst{21-19} = 0b011;
+  let Inst{18-16} = opc;
+  let Inst{15-13} = 0b100;
+  let Inst{12-10} = Pg;
+  let Inst{9-6}   = 0b0000;
+  let Inst{5}     = i1;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
+  def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
+  def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
+  def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
+}
+
+
+//===----------------------------------------------------------------------===//
 // SVE Stack Allocation Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_arith_vl<bit opc, string asm>
 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
   asm, "\t$Rd, $Rn, $imm6",
   "",
   []>, Sched<[]> {

test/MC/AArch64/SVE/fadd-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediates (must be 0.5 or 1.0)
+
+fadd z0.h, p0/m, z0.h, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
+// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd z0.h, p0/m, z0.h, #0.4999999999999999999999999
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
+// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.4999999999999999999999999
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd z0.h, p0/m, z0.h, #0.5000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
+// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd z0.h, p0/m, z0.h, #1.0000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
+// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
+// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fadd.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fadd    z0.h, p0/m, z0.h, #0.500000000000000
+// CHECK-INST: fadd    z0.h, p0/m, z0.h, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 58 65 <unknown>
+
+fadd    z0.h, p0/m, z0.h, #0.5
+// CHECK-INST: fadd    z0.h, p0/m, z0.h, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 58 65 <unknown>
+
+fadd    z0.s, p0/m, z0.s, #0.5
+// CHECK-INST: fadd    z0.s, p0/m, z0.s, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x98,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 98 65 <unknown>
+
+fadd    z0.d, p0/m, z0.d, #0.5
+// CHECK-INST: fadd    z0.d, p0/m, z0.d, #0.5
+// CHECK-ENCODING: [0x00,0x80,0xd8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 d8 65 <unknown>
+
+fadd    z31.h, p7/m, z31.h, #1.000000000000000
+// CHECK-INST: fadd    z31.h, p7/m, z31.h, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 58 65 <unknown>
+
+fadd    z31.h, p7/m, z31.h, #1.0
+// CHECK-INST: fadd    z31.h, p7/m, z31.h, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 58 65 <unknown>
+
+fadd    z31.s, p7/m, z31.s, #1.0
+// CHECK-INST: fadd    z31.s, p7/m, z31.s, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0x98,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 98 65 <unknown>
+
+fadd    z31.d, p7/m, z31.d, #1.0
+// CHECK-INST: fadd    z31.d, p7/m, z31.d, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>

test/MC/AArch64/SVE/fmax-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediates (must be 0.0 or 1.0)
+
+fmax z0.h, p0/m, z0.h, #0.5
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.0 or 1.0.
+// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.5
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax z0.h, p0/m, z0.h, #-0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #-0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax z0.h, p0/m, z0.h, #0.0000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.0 or 1.0.
+// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax z0.h, p0/m, z0.h, #1.0000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.0 or 1.0.
+// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.0 or 1.0.
+// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

test/MC/AArch64/SVE/fmax.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmax    z0.h, p0/m, z0.h, #0.000000000000000
+// CHECK-INST: fmax    z0.h, p0/m, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x80,0x5e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 5e 65 <unknown>
+
+fmax    z0.h, p0/m, z0.h, #0.0
+// CHECK-INST: fmax    z0.h, p0/m, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x80,0x5e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 5e 65 <unknown>
+
+fmax    z0.s, p0/m, z0.s, #0.0
+// CHECK-INST: fmax    z0.s, p0/m, z0.s, #0.0
+// CHECK-ENCODING: [0x00,0x80,0x9e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 9e 65 <unknown>
+
+fmax    z31.d, p7/m, z31.d, #1.0
+// CHECK-INST: fmax    z31.d, p7/m, z31.d, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0xde,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c de 65 <unknown>
+
+fmax    z31.h, p7/m, z31.h, #1.0
+// CHECK-INST: fmax    z31.h, p7/m, z31.h, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0x5e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 5e 65 <unknown>
+
+fmax    z31.s, p7/m, z31.s, #1.0
+// CHECK-INST: fmax    z31.s, p7/m, z31.s, #1.0
+// CHECK-ENCODING: [0x3f,0x9c,0x9e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 9e 65 <unknown>
+
+fmax    z0.d, p0/m, z0.d, #0.0
+// CHECK-INST: fmax    z0.d, p0/m, z0.d, #0.0
+// CHECK-ENCODING: [0x00,0x80,0xde,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 de 65 <unknown>

test/MC/AArch64/SVE/fmul-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediates (must be 0.5 or 2.0)
+
+fmul z0.h, p0/m, z0.h, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, p0/m, z0.h, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, p0/m, z0.h, #0.4999999999999999999999999
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.4999999999999999999999999
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, p0/m, z0.h, #0.5000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, p0/m, z0.h, #2.0000000000000000000000001
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #2.0000000000000000000000001
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, p0/m, z0.h, #1.9999999999999999999999999
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 2.0.
+// CHECK-NEXT: fmul z0.h, p0/m, z0.h, #1.9999999999999999999999999
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/fmul.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmul    z0.h, p0/m, z0.h, #0.5000000000000
+// CHECK-INST: fmul    z0.h, p0/m, z0.h, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
+
+fmul    z0.h, p0/m, z0.h, #0.5
+// CHECK-INST: fmul    z0.h, p0/m, z0.h, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
+
+fmul    z0.s, p0/m, z0.s, #0.5
+// CHECK-INST: fmul    z0.s, p0/m, z0.s, #0.5
+// CHECK-ENCODING: [0x00,0x80,0x9a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 9a 65 <unknown>
+
+fmul    z0.d, p0/m, z0.d, #0.5
+// CHECK-INST: fmul    z0.d, p0/m, z0.d, #0.5
+// CHECK-ENCODING: [0x00,0x80,0xda,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 da 65 <unknown>
+
+fmul    z31.h, p7/m, z31.h, #2.0
+// CHECK-INST: fmul    z31.h, p7/m, z31.h, #2.0
+// CHECK-ENCODING: [0x3f,0x9c,0x5a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 5a 65 <unknown>
+
+fmul    z31.s, p7/m, z31.s, #2.0
+// CHECK-INST: fmul    z31.s, p7/m, z31.s, #2.0
+// CHECK-ENCODING: [0x3f,0x9c,0x9a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c 9a 65 <unknown>
+
+fmul    z31.d, p7/m, z31.d, #2.0
+// CHECK-INST: fmul    z31.d, p7/m, z31.d, #2.0
+// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 3f 9c da 65 <unknown>