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Check Sched Class tables at generation time
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Authored by avt77 on Jun 1 2018, 8:17 AM.

Details

Summary

Some .td files have instrs/instregex items which are not necessary. Sometimes we have overridding of an instruction but there are no changes; sometimes we completly override Sched Class and it means we should use the new specific class instead of the current one; etc. For example see PR35548. This patch fixes some of such issues.
The source code is almost completely prepared by Simon Pilgrim - I only adopted it for publishing. The patch does not have any tests but if aply it and launch TableGen you'll see warnings like here:
warning:Model 'ThunderX2T99Model' completely overrides class 'WriteSTIdx_ReadAdrBase' for instrs:
warning: STRBBroW
warning: STRBBroX
warning: STRBroW

or

warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZB' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZBo' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZH' on model: 'P9Model'

or

warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOP' from 'WriteJump'
warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOPE' from 'WriteJump'
warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOPNE' from 'WriteJump'

Diff Detail

Event Timeline

avt77 created this revision.Jun 1 2018, 8:17 AM
avt77 added a comment.Jun 5 2018, 7:39 AM

Something is wrong with current diagnostic. Fro example, we have

warning:Model 'AtomModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'BroadwellModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'BtVer2Model' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SkylakeServerModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SandyBridgeModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'HaswellModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SLMModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SkylakeClientModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'Znver1Model' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int

But that's exactly what we wanted for 'WriteFDiv64':

  • we have some abstarct on high level
  • we implement some intrs using the abstract
  • we override the abstract for every target model

It seems we don't need any warn here.

avt77 added a comment.Jun 5 2018, 7:58 AM

Next, we have for P9Model only:

warning:Model 'P9Model' unnecessarily overrides instruction 'EVSUBFW' from 'IIC_VecFP'
warning:Model 'P9Model' unnecessarily overrides instruction 'EVSUBIFW' from 'IIC_VecFP'
warning:Model 'P9Model' unnecessarily overrides instruction 'EVXOR' from 'IIC_VecFP'

What does it mean? I don't understand the logic.

avt77 added a comment.Jun 5 2018, 8:02 AM

And the last question. Again, in P9Model we have

warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTFPo' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTSB' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTSBo' on model: 'P9Model'

What does it mean? Could you clarify this issue?

avt77 added a comment.Jun 7 2018, 6:03 AM

Simon, I have some troubles with slack connection that's why I read your message only now :-( I'll back with answer asap.

avt77 added a comment.Jun 7 2018, 6:13 AM

If I use one check only (" // Check if an instruction is always overriden (candidate for a new class?)") I see warnings for p9model only.
At the moment, I'm learning debug output related to generation of all these tables and hope to come up with some realistic logging soon.

RKSimon added a subscriber: llvm-commits.
RKSimon added inline comments.
utils/TableGen/SubtargetEmitter.cpp
1285

I think this patch should be limited to just this warning and remove the other check loops below for future patches - after we've at least cleaned up these 'unnecessary overrides' from the scheduler models.

lebedev.ri added inline comments.Jun 18 2018, 7:26 AM
utils/TableGen/SubtargetEmitter.cpp
1272–1278

This is conspiciously similar to the operator== of MCSchedClassDesc.
And is subtly different. This does not look at ReadAdvanceIdx, NumWriteLatencyEntries.
I would strongly suggest to:

  bool EqualityCompare(const MCSchedClassDesc &RHS, bool IgnoreReadAdvance = false) const {
    return (NumMicroOps == RHS.NumMicroOps && BeginGroup == RHS.BeginGroup &&
           EndGroup == RHS.EndGroup && WriteProcResIdx == RHS.WriteProcResIdx &&
           NumWriteProcResEntries == RHS.NumWriteProcResEntries &&
           WriteLatencyIdx == RHS.WriteLatencyIdx &&
           NumWriteLatencyEntries == RHS.NumWriteLatencyEntries) &&
           (IgnoreReadAdvance ||
           (ReadAdvanceIdx == RHS.ReadAdvanceIdx && NumReadAdvanceEntries == RHS.NumReadAdvanceEntries)));
  }
  bool operator==(const MCSchedClassDesc &RHS) const {
    return EqualityCompare(RHS, /*IgnoreReadAdvance=*/false);
  }
...
  if (Orig.NumReadAdvanceEntries && !Inst.NumReadAdvanceEntries) {
    return EqualityCompare(RHS, /*IgnoreReadAdvance=*/true);

Anything to do to get this going? Or did this got replaced by some other differential? D48222?

Anything to do to get this going? Or did this got replaced by some other differential? D48222?

I supposed to replace this patch with D48222 but maibe it's better to combine them? Let's leave this patch for a while - we'll see if it's possible to combine.

lebedev.ri requested changes to this revision.Jul 10 2019, 3:30 PM

(removing from my review queue)

This revision now requires changes to proceed.Jul 10 2019, 3:30 PM