Check Sched Class tables at generation time

[RKSimon]

Summary

Some .td files have instrs/instregex items which are not necessary. Sometimes we have overridding of an instruction but there are no changes; sometimes we completly override Sched Class and it means we should use the new specific class instead of the current one; etc. For example see PR35548. This patch fixes some of such issues.
The source code is almost completely prepared by Simon Pilgrim - I only adopted it for publishing. The patch does not have any tests but if aply it and launch TableGen you'll see warnings like here:
warning:Model 'ThunderX2T99Model' completely overrides class 'WriteSTIdx_ReadAdrBase' for instrs:
warning: STRBBroW
warning: STRBBroX
warning: STRBroW

or

warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZB' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZBo' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPNEZH' on model: 'P9Model'

or

warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOP' from 'WriteJump'
warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOPE' from 'WriteJump'
warning:Model 'SandyBridgeModel' unnecessarily overrides instruction 'LOOPNE' from 'WriteJump'

[avt77]

Something is wrong with current diagnostic. Fro example, we have

warning:Model 'AtomModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'BroadwellModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'BtVer2Model' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SkylakeServerModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SandyBridgeModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'HaswellModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SLMModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'SkylakeClientModel' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int
warning:Model 'Znver1Model' completely overrides class 'WriteFDiv64' for instrs:
warning: DIVSDrr
warning: DIVSDrr_Int
warning: VDIVSDZrr
warning: VDIVSDZrr_Int
warning: VDIVSDZrr_Intk
warning: VDIVSDZrr_Intkz
warning: VDIVSDZrrb_Int
warning: VDIVSDZrrb_Intk
warning: VDIVSDZrrb_Intkz
warning: VDIVSDrr
warning: VDIVSDrr_Int

But that's exactly what we wanted for 'WriteFDiv64':

• we have some abstarct on high level
• we implement some intrs using the abstract
• we override the abstract for every target model

It seems we don't need any warn here.

[avt77]

Next, we have for P9Model only:

warning:Model 'P9Model' unnecessarily overrides instruction 'EVSUBFW' from 'IIC_VecFP'
warning:Model 'P9Model' unnecessarily overrides instruction 'EVSUBIFW' from 'IIC_VecFP'
warning:Model 'P9Model' unnecessarily overrides instruction 'EVXOR' from 'IIC_VecFP'

What does it mean? I don't understand the logic.

[avt77]

And the last question. Again, in P9Model we have

warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTFPo' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTSB' on model: 'P9Model'
warning:Class 'IIC_VecFPCompare' never uses instruction 'VCMPGTSBo' on model: 'P9Model'

What does it mean? Could you clarify this issue?

[avt77]

Simon, I have some troubles with slack connection that's why I read your message only now :-( I'll back with answer asap.

[avt77]

If I use one check only (" // Check if an instruction is always overriden (candidate for a new class?)") I see warnings for p9model only.
At the moment, I'm learning debug output related to generation of all these tables and hope to come up with some realistic logging soon.

[RKSimon]

utils/TableGen/SubtargetEmitter.cpp

1285

I think this patch should be limited to just this warning and remove the other check loops below for future patches - after we've at least cleaned up these 'unnecessary overrides' from the scheduler models.

[lebedev.ri]

utils/TableGen/SubtargetEmitter.cpp

1272–1278

This is conspiciously similar to the operator== of MCSchedClassDesc.
And is subtly different. This does not look at ReadAdvanceIdx, NumWriteLatencyEntries.
I would strongly suggest to:

  bool EqualityCompare(const MCSchedClassDesc &RHS, bool IgnoreReadAdvance = false) const {
    return (NumMicroOps == RHS.NumMicroOps && BeginGroup == RHS.BeginGroup &&
           EndGroup == RHS.EndGroup && WriteProcResIdx == RHS.WriteProcResIdx &&
           NumWriteProcResEntries == RHS.NumWriteProcResEntries &&
           WriteLatencyIdx == RHS.WriteLatencyIdx &&
           NumWriteLatencyEntries == RHS.NumWriteLatencyEntries) &&
           (IgnoreReadAdvance ||
           (ReadAdvanceIdx == RHS.ReadAdvanceIdx && NumReadAdvanceEntries == RHS.NumReadAdvanceEntries)));
  }
  bool operator==(const MCSchedClassDesc &RHS) const {
    return EqualityCompare(RHS, /*IgnoreReadAdvance=*/false);
  }
...
  if (Orig.NumReadAdvanceEntries && !Inst.NumReadAdvanceEntries) {
    return EqualityCompare(RHS, /*IgnoreReadAdvance=*/true);

[lebedev.ri]

Anything to do to get this going? Or did this got replaced by some other differential? D48222?

[avt77]

In D47637#1162704, @lebedev.ri wrote:

Anything to do to get this going? Or did this got replaced by some other differential? D48222?

I supposed to replace this patch with D48222 but maibe it's better to combine them? Let's leave this patch for a while - we'll see if it's possible to combine.

[lebedev.ri]

(removing from my review queue)

[RKSimon]

Commandeering this old patch - I have various local patches that this was based on that I'd like to get upstreamed

include/llvm/MC/MCSchedule.h

#endif
   uint16_t NumReadAdvanceEntries;
 
   bool isValid() const {
     return NumMicroOps != InvalidNumMicroOps;
   }
   bool isVariant() const {
     return NumMicroOps == VariantNumMicroOps;
   }
+  bool operator==(const MCSchedClassDesc &RHS) const {
+    return NumMicroOps == RHS.NumMicroOps && BeginGroup == RHS.BeginGroup &&
+           EndGroup == RHS.EndGroup && WriteProcResIdx == RHS.WriteProcResIdx &&
+           NumWriteProcResEntries == RHS.NumWriteProcResEntries &&
+           WriteLatencyIdx == RHS.WriteLatencyIdx &&
+           NumWriteLatencyEntries == RHS.NumWriteLatencyEntries &&
+           ReadAdvanceIdx == RHS.ReadAdvanceIdx &&
+           NumReadAdvanceEntries == RHS.NumReadAdvanceEntries;
+  }
 };
 
 /// Specify the cost of a register definition in terms of number of physical
 /// register allocated at register renaming stage. For example, AMD Jaguar.
 /// natively supports 128-bit data types, and operations on 256-bit registers
 /// (i.e. YMM registers) are internally split into two COPs (complex operations)
 /// and each COP updates a physical register. Basically, on Jaguar, a YMM
 /// register write effectively consumes two physical registers. That means,

utils/TableGen/CodeGenSchedule.h

class CodeGenSchedModels {
   // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
   unsigned NumInstrSchedClasses;
 
   RecVec ProcResourceDefs;
   RecVec ProcResGroups;
 
   // Map each instruction to its unique SchedClass index considering the
   // combination of it's itinerary class, SchedRW list, and InstRW records.
-  using InstClassMapTy = DenseMap<Record*, unsigned>;
+  // Stores both the original SchedRW class index, and the InstRW override.
+  using InstClassMapTy = DenseMap<Record *, std::pair<unsigned, unsigned>>;
   InstClassMapTy InstrClassMap;
 
 public:
   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 
   // iterator access to the scheduling classes.
   using class_iterator = std::vector<CodeGenSchedClass>::iterator;
   using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
     return SchedClasses[Idx];
   }
 
   // Get the SchedClass index for an instruction. Instructions with no
   // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
   // for NoItinerary.
   unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
 
+  // Get the original and InstRW SchedClass indices for an instruction.
+  // Instructions with no itinerary, no SchedReadWrites, and no InstrReadWrites
+  // references return 0 for NoItinerary.
+  std::pair<unsigned, unsigned>
+  getSchedClassIdxPair(const CodeGenInstruction &Inst) const;
+
   using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
   SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
   SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
   ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
 
   unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
 
   void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;

utils/TableGen/CodeGenSchedule.cpp

void CodeGenSchedModels::collectSchedClasses() {
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
     Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
     IdxVec Writes, Reads;
     if (!Inst->TheDef->isValueUnset("SchedRW"))
       findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
 
     // ProcIdx == 0 indicates the class applies to all processors.
     unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
-    InstrClassMap[Inst->TheDef] = SCIdx;
+    InstrClassMap[Inst->TheDef] = std::make_pair(SCIdx, SCIdx);
   }
   // Create classes for InstRW defs.
   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
   llvm::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
   LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
   for (Record *RWDef : InstRWDefs)
     createInstRWClass(RWDef);
 
LLVM_DEBUG({
       }
     });
   }
 }
 
 // Get the SchedClass index for an instruction.
 unsigned
 CodeGenSchedModels::getSchedClassIdx(const CodeGenInstruction &Inst) const {
+  return InstrClassMap.lookup(Inst.TheDef).second;
+}
+
+std::pair<unsigned, unsigned>
+CodeGenSchedModels::getSchedClassIdxPair(const CodeGenInstruction &Inst) const {
   return InstrClassMap.lookup(Inst.TheDef);
 }
 
 std::string
 CodeGenSchedModels::createSchedClassName(Record *ItinClassDef,
                                          ArrayRef<unsigned> OperWrites,
                                          ArrayRef<unsigned> OperReads) {
 
void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
   const RecVec *InstDefs = Sets.expand(InstRWDef);
   if (InstDefs->empty())
     PrintFatalError(InstRWDef->getLoc(), "No matching instruction opcodes");
 
   for (Record *InstDef : *InstDefs) {
     InstClassMapTy::const_iterator Pos = InstrClassMap.find(InstDef);
     if (Pos == InstrClassMap.end())
       PrintFatalError(InstDef->getLoc(), "No sched class for instruction.");
-    unsigned SCIdx = Pos->second;
+    unsigned SCIdx = Pos->second.second;
     ClassInstrs[SCIdx].push_back(InstDef);
   }
   // For each set of Instrs, create a new class if necessary, and map or remap
   // the Instrs to it.
   for (auto &Entry : ClassInstrs) {
     unsigned OldSCIdx = Entry.first;
     ArrayRef<Record*> InstDefs = Entry.second;
     // If the all instrs in the current class are accounted for, then leave
     // them mapped to their old class.
     if (OldSCIdx) {
       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
       if (!RWDefs.empty()) {
         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
-        unsigned OrigNumInstrs =
-          count_if(*OrigInstDefs, [&](Record *OIDef) {
-                     return InstrClassMap[OIDef] == OldSCIdx;
-                   });
+        unsigned OrigNumInstrs = count_if(*OrigInstDefs, [&](Record *OIDef) {
+          return InstrClassMap[OIDef].second == OldSCIdx;
         if (OrigNumInstrs == InstDefs.size()) {
           assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
                  "expected a generic SchedClass");
           Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
           // Make sure we didn't already have a InstRW containing this
           // instruction on this model.
           for (Record *RWD : RWDefs) {
             if (RWD->getValueAsDef("SchedModel") == RWModelDef &&
if (OldSCIdx) {
         }
         assert(OldRWDef != InstRWDef &&
                "SchedClass has duplicate InstRW def");
         SC.InstRWs.push_back(OldRWDef);
       }
     }
     // Map each Instr to this new class.
     for (Record *InstDef : InstDefs)
-      InstrClassMap[InstDef] = SCIdx;
+      InstrClassMap[InstDef].second = SCIdx;
     SC.InstRWs.push_back(InstRWDef);
   }
 }
 
 // True if collectProcItins found anything.
 bool CodeGenSchedModels::hasItineraries() const {
   for (const CodeGenProcModel &PM : make_range(procModelBegin(),procModelEnd()))
     if (PM.hasItineraries())

 /// Infer classes from per-processor InstReadWrite definitions.
 void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
   for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) {
     assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!");
     Record *Rec = SchedClasses[SCIdx].InstRWs[I];
     const RecVec *InstDefs = Sets.expand(Rec);
     RecIter II = InstDefs->begin(), IE = InstDefs->end();
     for (; II != IE; ++II) {
-      if (InstrClassMap[*II] == SCIdx)
+      if (InstrClassMap[*II].second == SCIdx)
         break;
     }
     // If this class no longer has any instructions mapped to it, it has become
     // irrelevant.
     if (II == IE)
       continue;
     IdxVec Writes, Reads;
     findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);

utils/TableGen/SubtargetEmitter.cpp

 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend emits subtarget enumerations.
 //
 //===----------------------------------------------------------------------===//
 
-#include "CodeGenTarget.h"
 #include "CodeGenSchedule.h"
+#include "CodeGenTarget.h"
 #include "PredicateExpander.h"
-#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/APInt.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Error.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 #include <map>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "subtarget-emitter"
 
+#ifdef EXPENSIVE_CHECKS
+// FIXME: TableGen is failed iff EXPENSIVE_CHECKS defined
+static constexpr bool OptCheckSchedClassTable = true;
+#else
+// FIXME: the default value should be false
+static cl::opt<bool> OptCheckSchedClassTable(
+    "check-sched-class-table", cl::init(true), cl::Hidden,
+    cl::desc("Check sched class table on different types of inconsistencies"));
+#endif
+
 namespace {
 
 class SubtargetEmitter {
   // Each processor has a SchedClassDesc table with an entry for each SchedClass.
   // The SchedClassDesc table indexes into a global write resource table, write
   // latency table, and read advance table.
   struct SchedClassTables {
     std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
class SubtargetEmitter {
   Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
                              const CodeGenProcModel &ProcModel);
   Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
                           const CodeGenProcModel &ProcModel);
   void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
                            const CodeGenProcModel &ProcModel);
   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
                            SchedClassTables &SchedTables);
+  void CheckSchedClassTables(SchedClassTables &SchedTables);
   void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
   void EmitProcessorModels(raw_ostream &OS);
   void EmitProcessorLookup(raw_ostream &OS);
   void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
   void emitSchedModelHelpersImpl(raw_ostream &OS,
                                  bool OnlyExpandMCInstPredicates = false);
   void emitGenMCSubtargetInfo(raw_ostream &OS);
 
for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
     else {
       SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
       SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
                                             ReadAdvanceEntries.end());
     }
   }
 }
 
+// Check SchedClass tables for unnecessary duplication.
+void SubtargetEmitter::CheckSchedClassTables(SchedClassTables &SchedTables) {
+  if (!OptCheckSchedClassTable)
+    return;
+  ArrayRef<CodeGenSchedClass> SchedClasses = SchedModels.schedClasses();
+  unsigned NumInstrSchedClasses = SchedModels.numInstrSchedClasses();
+  unsigned NumProcModels = SchedModels.procModels().size();
+
+  std::string str;
+  raw_string_ostream OS(str);
+
+  // Tag which classes are overriden.
+  SmallVector<APInt, 16> OverriddenSC(
+      NumProcModels, APInt::getAllOnesValue(NumInstrSchedClasses));
+
+  // Check if the 2 MCSchedClassDesc are either identical or only differ
+  // by ReadAdvanceEntries (x86 overrides are often missing these).
+  auto IsEquivalent = [&SchedTables](const CodeGenProcModel &PM,
+                                     const MCSchedClassDesc &Orig,
+                                     const MCSchedClassDesc &Inst) {
+    if (Orig == Inst)
+      return true;
+    if (Orig.NumReadAdvanceEntries && !Inst.NumReadAdvanceEntries) {
+      return Orig.NumMicroOps == Inst.NumMicroOps &&
+             Orig.BeginGroup == Inst.BeginGroup &&
+             Orig.EndGroup == Inst.EndGroup &&
+             Orig.WriteProcResIdx == Inst.WriteProcResIdx &&
+             Orig.NumWriteProcResEntries == Inst.NumWriteProcResEntries &&
+             Orig.WriteLatencyIdx == Inst.WriteLatencyIdx &&
+             Orig.NumWriteLatencyEntries == Inst.NumWriteLatencyEntries;
+    }
+    return false;
+  };
+
+  // Check each instruction for each model to see if its overridden but has
+  // the same schedule as its default class.
+  for (const CodeGenInstruction *Inst : TGT.getInstructionsByEnumValue()) {
+    const std::pair<unsigned, unsigned> ScIdx =
+        SchedModels.getSchedClassIdxPair(*Inst);
+    if (ScIdx.first == 0)
+      continue;
+
+    const CodeGenSchedClass &CgOrig = SchedClasses[ScIdx.first];
+    const CodeGenSchedClass &CgInst = SchedClasses[ScIdx.second];
+
+    for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
+                                      PE = SchedModels.procModelEnd();
+         PI != PE; ++PI) {
+      unsigned ProcIdx = PI - SchedModels.procModelBegin();
+      if (!PI->hasInstrSchedModel())
+        continue;
+
+      std::vector<MCSchedClassDesc> &SCTab =
+          SchedTables.ProcSchedClasses[1 + ProcIdx];
+      if (SCTab.size() != NumInstrSchedClasses)
+        continue;
+
+      if (ScIdx.first == ScIdx.second) {
+        OverriddenSC[ProcIdx].clearBit(ScIdx.first);
+        continue;
+      }
+
+      const MCSchedClassDesc &ScOrig = SCTab[ScIdx.first];
+      const MCSchedClassDesc &ScInst = SCTab[ScIdx.second];
+      if (IsEquivalent(*PI, ScOrig, ScInst)) {
+        OverriddenSC[ProcIdx].clearBit(ScIdx.first);
+
+        for (const Record *InstrRW : CgInst.InstRWs) {
+          const Record *InstModelDef = InstrRW->getValueAsDef("SchedModel");
+          if (InstModelDef->getName() == PI->ModelName) {
+            OS << "Model '" << PI->ModelName
+               << "' unnecessarily overrides instruction '"
+               << Inst->TheDef->getName() << "' from '" << CgOrig.Name;
+            PrintWarning(OS.str());
+            str.clear();
+          }
+        }
+      }
+    }
+  }
+  // Check if an instruction is always overriden (candidate for a new class?).
+  for (unsigned ScIdx = 1; ScIdx < NumInstrSchedClasses; ++ScIdx) {
+    const CodeGenSchedClass &CgSc = SchedClasses[ScIdx];
+    for (const CodeGenInstruction *Inst : TGT.getInstructionsByEnumValue()) {
+      const std::pair<unsigned, unsigned> ScPair =
+          SchedModels.getSchedClassIdxPair(*Inst);
+      if (ScPair.first == ScIdx && ScPair.second != ScIdx) {
+        for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
+                                          PE = SchedModels.procModelEnd();
+             PI != PE; ++PI) {
+          unsigned ProcIdx = PI - SchedModels.procModelBegin();
+          if (!PI->hasInstrSchedModel())
+            continue;
+
+          std::vector<MCSchedClassDesc> &SCTab =
+              SchedTables.ProcSchedClasses[1 + ProcIdx];
+          if (SCTab.size() != NumInstrSchedClasses)
+            continue;
+
+          const MCSchedClassDesc &ScOrig = SCTab[ScPair.first];
+          const MCSchedClassDesc &ScInst = SCTab[ScPair.second];
+          if (!IsEquivalent(*PI, ScOrig, ScInst)) {
+            OS << "Class '" << CgSc.Name << "' never uses instruction '"
+               << Inst->TheDef->getName() << "' on model: '" << PI->ModelName;
+            PrintWarning(OS.str());
+            str.clear();
+          }
+        }
+      }
+    }
+  }
+  // Check if a model never uses the default class - overriding all
+  // instructions.
+  for (unsigned ScIdx = 1; ScIdx < NumInstrSchedClasses; ++ScIdx) {
+    const CodeGenSchedClass &CgSc = SchedClasses[ScIdx];
+    if (!StringRef(CgSc.Name).startswith("Write"))
+      continue;
+
+    for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
+                                      PE = SchedModels.procModelEnd();
+         PI != PE; ++PI) {
+      unsigned ProcIdx = PI - SchedModels.procModelBegin();
+      if (!PI->hasInstrSchedModel())
+        continue;
+      if (OverriddenSC[ProcIdx][ScIdx]) {
+        OS << "Model '" << PI->ModelName << "' completely overrides class '"
+           << CgSc.Name << "' for instrs:";
+        PrintWarning(OS.str());
+        str.clear();
+        for (const CodeGenInstruction *Inst :
+             TGT.getInstructionsByEnumValue()) {
+          if (SchedModels.getSchedClassIdxPair(*Inst).first == ScIdx) {
+            PrintWarning({"\t", Inst->TheDef->getName()});
+          }
+        }
+      }
+    }
+  }
+}
+
 // Emit SchedClass tables for all processors and associated global tables.
 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
                                             raw_ostream &OS) {
   // Emit global WriteProcResTable.
   OS << "\n// {ProcResourceIdx, Cycles}\n"
      << "extern const llvm::MCWriteProcResEntry "
      << Target << "WriteProcResTable[] = {\n"
      << "  { 0,  0}, // Invalid\n";
void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
   }
   OS << "\n// ===============================================================\n"
      << "// Data tables for the new per-operand machine model.\n";
 
   SchedClassTables SchedTables;
   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
     GenSchedClassTables(ProcModel, SchedTables);
   }
+  CheckSchedClassTables(SchedTables);
   EmitSchedClassTables(SchedTables, OS);
 
   // Emit the processor machine model
   EmitProcessorModels(OS);
   // Emit the processor lookup data
   EmitProcessorLookup(OS);
 
   OS << "\n#undef DBGFIELD";