[AArch64][SVE] Asm: Print indexed element 0 as FPR.

[sdesmalen]

Summary

Print the first indexed element as a FP register,
for example:

mov z0.d, z1.d[0]

Is now printed as:

mov z0.d, d1

[fhahn]

LGTM. It also adds aliases for FPR-to-ZPR versions, maybe you could mention that in the commit message?

llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td

 
 def ZPRAny  : ZPRRegOp<"",  ZPRAsmOpAny, ZPR>;
 def ZPR8    : ZPRRegOp<"b", ZPRAsmOp8,   ZPR>;
 def ZPR16   : ZPRRegOp<"h", ZPRAsmOp16,  ZPR>;
 def ZPR32   : ZPRRegOp<"s", ZPRAsmOp32,  ZPR>;
 def ZPR64   : ZPRRegOp<"d", ZPRAsmOp64,  ZPR>;
 def ZPR128  : ZPRRegOp<"q", ZPRAsmOp128, ZPR>;
 
+class FPRasZPR<int Width> : AsmOperandClass{
+  let Name = "FPR" # Width # "asZPR";
+  let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
+  let RenderMethod = "addFPRasZPRRegOperands<" # Width # ">";
+}
+
+class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {
+  let ParserMatchClass = FPRasZPR<Width>;
+  let PrintMethod = "printZPRasFPR<" # Width # ">";
+}
+
+def FPR8asZPR   : FPRasZPROperand<8>;
+def FPR16asZPR  : FPRasZPROperand<16>;
+def FPR32asZPR  : FPRasZPROperand<32>;
+def FPR64asZPR  : FPRasZPROperand<64>;
+def FPR128asZPR : FPRasZPROperand<128>;
 
 let Namespace = "AArch64" in {
   def zsub0 : SubRegIndex<128, -1>;
   def zsub1 : SubRegIndex<128, -1>;
   def zsub2 : SubRegIndex<128, -1>;
   def zsub3 : SubRegIndex<128, -1>;
 }
 

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

template <unsigned Class> bool isSVEVectorReg() const {
     default:
       llvm_unreachable("Unsupport register class");
     }
 
     return (Kind == k_Register && Reg.Kind == RK) &&
            AArch64MCRegisterClasses[Class].contains(getReg());
   }
 
+  template <unsigned Class> bool isFPRasZPR() const {
+    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
+           AArch64MCRegisterClasses[Class].contains(getReg());
+  }
+
   template <int ElementWidth, unsigned Class>
   DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
     if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
       return DiagnosticPredicateTy::NoMatch;
 
     if (isSVEVectorReg<Class>() &&
            (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
       return DiagnosticPredicateTy::Match;
void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
 
     const MCRegisterInfo *RI = Ctx.getRegisterInfo();
     uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
         RI->getEncodingValue(getReg()));
 
     Inst.addOperand(MCOperand::createReg(Reg));
   }
 
+  template <int Width>
+  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
+    unsigned Base;
+    switch (Width) {
+    case 8:   Base = AArch64::B0; break;
+    case 16:  Base = AArch64::H0; break;
+    case 32:  Base = AArch64::S0; break;
+    case 64:  Base = AArch64::D0; break;
+    case 128: Base = AArch64::Q0; break;
+    default:
+      llvm_unreachable("Unsupported width");
+    }
+    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
+  }
+
   void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     assert(
         AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
     Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
   }
 
   void addVectorReg128Operands(MCInst &Inst, unsigned N) const {

llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

protected:
   template <typename T>
   void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &O);
   void printSVEPattern(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   template <char = 0>
   void printSVERegOp(const MCInst *MI, unsigned OpNum,
                     const MCSubtargetInfo &STI, raw_ostream &O);
+  template <int Width>
+  void printZPRasFPR(const MCInst *MI, unsigned OpNum,
+                     const MCSubtargetInfo &STI, raw_ostream &O);
 };
 
 class AArch64AppleInstPrinter : public AArch64InstPrinter {
 public:
   AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                           const MCRegisterInfo &MRI);
 
   void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,

llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
   // Prefer the default format for 16bit values, hex otherwise.
   if ((int16_t)PrintVal == (SignedT)PrintVal)
     printImmSVE((T)PrintVal, O);
   else if ((uint16_t)PrintVal == PrintVal)
     printImmSVE(PrintVal, O);
   else
     O << '#' << formatHex((uint64_t)PrintVal);
 }
+
+template <int Width>
+void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
+  unsigned Base;
+  switch (Width) {
+  case 8:   Base = AArch64::B0; break;
+  case 16:  Base = AArch64::H0; break;
+  case 32:  Base = AArch64::S0; break;
+  case 64:  Base = AArch64::D0; break;
+  case 128: Base = AArch64::Q0; break;
+  default:
+    llvm_unreachable("Unsupported width");
+  }
+  unsigned Reg = MI->getOperand(OpNum).getReg();
+  O << getRegisterName(Reg - AArch64::Z0 + Base);
+}

llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_int_perm_dup_i<string asm> {
   def : InstAlias<"mov $Zd, $Zn$idx",
                   (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>;
   def : InstAlias<"mov $Zd, $Zn$idx",
                   (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>;
   def : InstAlias<"mov $Zd, $Zn$idx",
                   (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>;
   def : InstAlias<"mov $Zd, $Zn$idx",
                   (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>;
+  def : InstAlias<"mov $Zd, $Bn",
+                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>;
+  def : InstAlias<"mov $Zd, $Hn",
+                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>;
+  def : InstAlias<"mov $Zd, $Sn",
+                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
+  def : InstAlias<"mov $Zd, $Dn",
+                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>;
+  def : InstAlias<"mov $Zd, $Qn",
+                  (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Logical Mask Immediate Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_log_imm<bits<2> opc, string asm>
 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),

llvm/trunk/test/MC/AArch64/SVE/dup-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [-128, 127] or a multiple of 256 in range [-32768, 32512]
 // CHECK-NEXT: dup z0.d, #128, lsl #8
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate not compatible with encode/decode function.
 
+dup z0.b, b0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: dup z0.b, b0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dup z0.h, h0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: dup z0.h, h0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dup z0.s, s0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: dup z0.s, s0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dup z0.d, d0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: dup z0.d, d0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dup z0.q, q0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: dup z0.q, q0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 dup z24.b, z17.b[-1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 63].
 // CHECK-NEXT: dup z24.b, z17.b[-1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 dup z17.b, z5.b[64]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 63].
 // CHECK-NEXT: dup z17.b, z5.b[64]

llvm/trunk/test/MC/AArch64/SVE/dup.s

 
 dup     z21.d, #32512
 // CHECK-INST: mov     z21.d, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: f5 ef f8 25 <unknown>
 
 dup     z0.b, z0.b[0]
-// CHECK-INST: mov     z0.b, z0.b[0]
+// CHECK-INST: mov     z0.b, b0
 // CHECK-ENCODING: [0x00,0x20,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 21 05 <unknown>
 
 dup     z0.h, z0.h[0]
-// CHECK-INST: mov     z0.h, z0.h[0]
+// CHECK-INST: mov     z0.h, h0
 // CHECK-ENCODING: [0x00,0x20,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 22 05 <unknown>
 
 dup     z0.s, z0.s[0]
-// CHECK-INST: mov     z0.s, z0.s[0]
+// CHECK-INST: mov     z0.s, s0
 // CHECK-ENCODING: [0x00,0x20,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 24 05 <unknown>
 
 dup     z0.d, z0.d[0]
-// CHECK-INST: mov     z0.d, z0.d[0]
+// CHECK-INST: mov     z0.d, d0
 // CHECK-ENCODING: [0x00,0x20,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 28 05 <unknown>
 
 dup     z0.q, z0.q[0]
-// CHECK-INST: mov     z0.q, z0.q[0]
+// CHECK-INST: mov     z0.q, q0
 // CHECK-ENCODING: [0x00,0x20,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 30 05 <unknown>
 
 dup     z31.b, z31.b[63]
 // CHECK-INST: mov     z31.b, z31.b[63]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve

llvm/trunk/test/MC/AArch64/SVE/mov.s

 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 15 70 df 05  <unknown>
 
 // --------------------------------------------------------------------------//
 // Tests for indexed variant
 
 mov     z0.b, z0.b[0]
-// CHECK-INST: mov     z0.b, z0.b[0]
+// CHECK-INST: mov     z0.b, b0
 // CHECK-ENCODING: [0x00,0x20,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 21 05 <unknown>
 
 mov     z0.h, z0.h[0]
-// CHECK-INST: mov     z0.h, z0.h[0]
+// CHECK-INST: mov     z0.h, h0
 // CHECK-ENCODING: [0x00,0x20,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 22 05 <unknown>
 
 mov     z0.s, z0.s[0]
-// CHECK-INST: mov     z0.s, z0.s[0]
+// CHECK-INST: mov     z0.s, s0
 // CHECK-ENCODING: [0x00,0x20,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 24 05 <unknown>
 
 mov     z0.d, z0.d[0]
-// CHECK-INST: mov     z0.d, z0.d[0]
+// CHECK-INST: mov     z0.d, d0
 // CHECK-ENCODING: [0x00,0x20,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 28 05 <unknown>
 
 mov     z0.q, z0.q[0]
-// CHECK-INST: mov     z0.q, z0.q[0]
+// CHECK-INST: mov     z0.q, q0
+// CHECK-ENCODING: [0x00,0x20,0x30,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 30 05 <unknown>
+
+mov     z0.b, b0
+// CHECK-INST: mov     z0.b, b0
+// CHECK-ENCODING: [0x00,0x20,0x21,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 21 05 <unknown>
+
+mov     z0.h, h0
+// CHECK-INST: mov     z0.h, h0
+// CHECK-ENCODING: [0x00,0x20,0x22,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 22 05 <unknown>
+
+mov     z0.s, s0
+// CHECK-INST: mov     z0.s, s0
+// CHECK-ENCODING: [0x00,0x20,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 24 05 <unknown>
+
+mov     z0.d, d0
+// CHECK-INST: mov     z0.d, d0
+// CHECK-ENCODING: [0x00,0x20,0x28,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 28 05 <unknown>
+
+mov     z0.q, q0
+// CHECK-INST: mov     z0.q, q0
 // CHECK-ENCODING: [0x00,0x20,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 30 05 <unknown>
 
 mov     z31.b, z31.b[63]
 // CHECK-INST: mov     z31.b, z31.b[63]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve