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Differential D47363

[AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
ClosedPublic

Authored by sdesmalen on May 25 2018, 2:33 AM.

Details

Reviewers
rengolin
huntergr
fhahn
samparker
SjoerdMeijer
javed.absar
Commits
rG26b9b2a8c392: [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
rL333414: [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
Summary

[AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.

This patch addresses the following variants:

  • bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'.
  • unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'.
  • predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'.

And also several aliases, such as:

  • ORN, alias of ORR.
  • EON, alias of EOR.
  • BIC, alias of AND (immediate variant)
  • MOV, alias of ORR (if unpredicated and source register operands are the same)

Diff Detail

Repository
rL LLVM

Event Timeline

sdesmalen created this revision.May 25 2018, 2:33 AM
Herald added a reviewer: javed.absar. · View Herald TranscriptMay 25 2018, 2:33 AM
Herald added subscribers: rkruppe, kristof.beyls, tschuett. · View Herald Transcript
fhahn accepted this revision.May 25 2018, 3:14 AM

LGTM, thanks

This revision is now accepted and ready to land.May 25 2018, 3:14 AM
Closed by commit rL333414: [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions. (authored by s.desmalen). · Explain WhyMay 29 2018, 6:12 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
19 lines
29 lines
test/
MC/
AArch64/
SVE/
19 lines
80 lines
67 lines
92 lines
52 lines
56 lines
67 lines
92 lines
18 lines
12 lines
52 lines
56 lines
67 lines
94 lines

Diff 148893

llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show All 9 Lines
// AArch64 Scalable Vector Extension (SVE) Instruction definitions. // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasSVE] in { let Predicates = [HasSVE] in {
defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">;
defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">;
defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">;
defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">;
defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
// Splat immediate (unpredicated) // Splat immediate (unpredicated)
defm DUP_ZI : sve_int_dup_imm<"dup">; defm DUP_ZI : sve_int_dup_imm<"dup">;
// continuous load with reg+immediate // continuous load with reg+immediate
defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>; defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>; defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>; defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>; defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
▲ Show 20 Lines • Show All 420 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE] in {
defm INDEX_RR : sve_int_index_rr<"index">; defm INDEX_RR : sve_int_index_rr<"index">;
defm INDEX_IR : sve_int_index_ir<"index">; defm INDEX_IR : sve_int_index_ir<"index">;
defm INDEX_RI : sve_int_index_ri<"index">; defm INDEX_RI : sve_int_index_ri<"index">;
defm INDEX_II : sve_int_index_ii<"index">; defm INDEX_II : sve_int_index_ii<"index">;
defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">; defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">;
defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">; defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
// InstAliases
def : InstAlias<"mov $Zd, $Zn",
(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
} }

llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 393 Lines • ▼ Show 20 Lines: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
let Inst{15-13} = 0b000; let Inst{15-13} = 0b000;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-5} = Zm; let Inst{9-5} = Zm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
} }
multiclass sve_int_bin_pred_log<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
}
multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
multiclass sve_int_arith_imm0<bits<3> opc, string asm> { multiclass sve_int_arith_imm0<bits<3> opc, string asm> {
def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>; def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>; def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>; def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
} }
//===----------------------------------------------------------------------===//
// SVE Bitwise Logical - Unpredicated Group
//===----------------------------------------------------------------------===//
class sve_int_bin_cons_log<bits<2> opc, string asm>
: I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),
asm, "\t$Zd, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = opc{1-0};
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-10} = 0b001100;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//SVE Index Generation Group //SVE Index Generation Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty, class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
Operand imm_ty> Operand imm_ty>
: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b), : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
asm, "\t$Zd, $imm5, $imm5b", asm, "\t$Zd, $imm5, $imm5b",
▲ Show 20 Lines • Show All 1,268 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s

Show All 40 Lines
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Source and Destination Registers must match // Source and Destination Registers must match
and z7.d, z8.d, #254 and z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: and z7.d, z8.d, #254 // CHECK-NEXT: and z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z7.d, z8.d, #254 and z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bic z7.d, z8.d, #254 // CHECK-NEXT: and z0.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
and z21.d, z5.d, z26.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: and z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate out of restricted predicate range
and z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/and.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
and z5.b, z5.b, #0xf9 and z5.b, z5.b, #0xf9
// CHECK-INST: and z5.b, z5.b, #0xf9 // CHECK-INST: and z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05] // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 80 05 <unknown> // CHECK-UNKNOWN: a5 2e 80 05 <unknown>
bic z5.b, z5.b, #0x06
// CHECK-INST: and z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
and z23.h, z23.h, #0xfff9 and z23.h, z23.h, #0xfff9
// CHECK-INST: and z23.h, z23.h, #0xfff9 // CHECK-INST: and z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 80 05 <unknown> // CHECK-UNKNOWN: b7 6d 80 05 <unknown>
bic z23.h, z23.h, #0x0006
// CHECK-INST: and z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
and z0.s, z0.s, #0xfffffff9 and z0.s, z0.s, #0xfffffff9
// CHECK-INST: and z0.s, z0.s, #0xfffffff9 // CHECK-INST: and z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 80 05 <unknown> // CHECK-UNKNOWN: a0 eb 80 05 <unknown>
bic z0.s, z0.s, #0x00000006
// CHECK-INST: and z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
and z0.d, z0.d, #0xfffffffffffffff9 and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] // CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 83 05 <unknown> // CHECK-UNKNOWN: a0 ef 83 05 <unknown>
bic z0.d, z0.d, #0x0000000000000006 and z5.b, z5.b, #0x6
// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: and z5.b, z5.b, #0x6
// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] // CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 83 05 <unknown> // CHECK-UNKNOWN: 25 3e 80 05 <unknown>
and z23.h, z23.h, #0x6
// CHECK-INST: and z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
and z0.s, z0.s, #0x6
// CHECK-INST: and z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
and z0.d, z0.d, #0x6
// CHECK-INST: and z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
and z0.d, z0.d, z0.d
// CHECK-INST: and z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 30 20 04 <unknown>
and z23.d, z13.d, z8.d
// CHECK-INST: and z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x31,0x28,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 31 28 04 <unknown>
and z31.b, p7/m, z31.b, z31.b
// CHECK-INST: and z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x1a,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 1a 04 <unknown>
and z31.h, p7/m, z31.h, z31.h
// CHECK-INST: and z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x5a,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 5a 04 <unknown>
and z31.s, p7/m, z31.s, z31.s
// CHECK-INST: and z31.s, p7/m, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0x9a,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 9a 04 <unknown>
and z31.d, p7/m, z31.d, z31.d
// CHECK-INST: and z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f da 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate not compatible with encode/decode function.
bic z5.b, z5.b, #0xfa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.b, z5.b, #0xfa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z5.b, z5.b, #0xfff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.b, z5.b, #0xfff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z5.h, z5.h, #0xfffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.h, z5.h, #0xfffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z5.h, z5.h, #0xfffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.h, z5.h, #0xfffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z5.s, z5.s, #0xfffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.s, z5.s, #0xfffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z5.s, z5.s, #0xffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z5.s, z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z15.d, z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: bic z15.d, z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bic z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bic z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bic z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bic z0.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
bic z21.d, z5.d, z26.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bic z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate out of restricted predicate range
bic z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/bic.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bic z5.b, z5.b, #0xf9
// CHECK-INST: and z5.b, z5.b, #0x6
// CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 3e 80 05 <unknown>
bic z23.h, z23.h, #0xfff9
// CHECK-INST: and z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
bic z0.s, z0.s, #0xfffffff9
// CHECK-INST: and z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
bic z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: and z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
bic z5.b, z5.b, #0x6
// CHECK-INST: and z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
bic z23.h, z23.h, #0x6
// CHECK-INST: and z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
bic z0.s, z0.s, #0x6
// CHECK-INST: and z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
bic z0.d, z0.d, #0x6
// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
bic z0.d, z0.d, z0.d
// CHECK-INST: bic z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
bic z23.d, z13.d, z8.d
// CHECK-INST: bic z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x31,0xe8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 31 e8 04 <unknown>
bic z31.b, p7/m, z31.b, z31.b
// CHECK-INST: bic z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x1b,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 1b 04 <unknown>
bic z31.h, p7/m, z31.h, z31.h
// CHECK-INST: bic z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x5b,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 5b 04 <unknown>
bic z31.s, p7/m, z31.s, z31.s
// CHECK-INST: bic z31.s, p7/m, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0x9b,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 9b 04 <unknown>
bic z31.d, p7/m, z31.d, z31.d
// CHECK-INST: bic z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f db 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE/eon-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate not compatible with encode/decode function.
eon z5.b, z5.b, #0xfa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.b, z5.b, #0xfa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z5.b, z5.b, #0xfff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.b, z5.b, #0xfff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z5.h, z5.h, #0xfffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.h, z5.h, #0xfffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z5.h, z5.h, #0xfffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.h, z5.h, #0xfffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z5.s, z5.s, #0xfffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.s, z5.s, #0xfffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z5.s, z5.s, #0xffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z5.s, z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z15.d, z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eon z15.d, z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
eon z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eon z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eon z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eon z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/eon.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eon z5.b, z5.b, #0xf9
// CHECK-INST: eor z5.b, z5.b, #0x6
// CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
eon z23.h, z23.h, #0xfff9
// CHECK-INST: eor z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
eon z0.s, z0.s, #0xfffffff9
// CHECK-INST: eor z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
eon z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: eor z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
eon z5.b, z5.b, #0x6
// CHECK-INST: eor z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
eon z23.h, z23.h, #0x6
// CHECK-INST: eor z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
eon z0.s, z0.s, #0x6
// CHECK-INST: eor z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
eon z0.d, z0.d, #0x6
// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 43 05 <unknown>

llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate not compatible with encode/decode function.
eor z5.b, z5.b, #0xfa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.b, z5.b, #0xfa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z5.b, z5.b, #0xfff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.b, z5.b, #0xfff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z5.h, z5.h, #0xfffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.h, z5.h, #0xfffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z5.h, z5.h, #0xfffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.h, z5.h, #0xfffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z5.s, z5.s, #0xfffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.s, z5.s, #0xfffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z5.s, z5.s, #0xffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z5.s, z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z15.d, z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: eor z15.d, z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
eor z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eor z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eor z0.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
eor z21.d, z5.d, z26.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate out of restricted predicate range
eor z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/eor.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eor z5.b, z5.b, #0xf9
// CHECK-INST: eor z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
eor z23.h, z23.h, #0xfff9
// CHECK-INST: eor z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
eor z0.s, z0.s, #0xfffffff9
// CHECK-INST: eor z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
eor z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
eor z5.b, z5.b, #0x6
// CHECK-INST: eor z5.b, z5.b, #0x6
// CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
eor z23.h, z23.h, #0x6
// CHECK-INST: eor z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
eor z0.s, z0.s, #0x6
// CHECK-INST: eor z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
eor z0.d, z0.d, #0x6
// CHECK-INST: eor z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
eor z23.d, z13.d, z8.d
// CHECK-INST: eor z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x31,0xa8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 31 a8 04 <unknown>
eor z0.d, z0.d, z0.d
// CHECK-INST: eor z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
eor z31.s, p7/m, z31.s, z31.s
// CHECK-INST: eor z31.s, p7/m, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0x99,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 99 04 <unknown>
eor z31.h, p7/m, z31.h, z31.h
// CHECK-INST: eor z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x59,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 59 04 <unknown>
eor z31.d, p7/m, z31.d, z31.d
// CHECK-INST: eor z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xd9,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f d9 04 <unknown>
eor z31.b, p7/m, z31.b, z31.b
// CHECK-INST: eor z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x19,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 19 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE/mov-diagnostics.s

Show All 14 Lines
// xzr is not a valid operand to mov // xzr is not a valid operand to mov
mov z0.d, xzr mov z0.d, xzr
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, xzr // CHECK-NEXT: mov z0.d, xzr
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Unpredicated mov of Z register only allowed for .d
mov z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediates // Invalid immediates
mov z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b mov z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [-128, 255] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [-128, 255]
// CHECK-NEXT: mov z0.b, #0, lsl #8 // CHECK-NEXT: mov z0.b, #0, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.b, #-129 mov z0.b, #-129
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE/mov.s

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
// CHECK-UNKNOWN: ff 3b e0 05 <unknown> // CHECK-UNKNOWN: ff 3b e0 05 <unknown>
mov z31.b, wsp mov z31.b, wsp
// CHECK-INST: mov z31.b, wsp // CHECK-INST: mov z31.b, wsp
// CHECK-ENCODING: [0xff,0x3b,0x20,0x05] // CHECK-ENCODING: [0xff,0x3b,0x20,0x05]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 3b 20 05 <unknown> // CHECK-UNKNOWN: ff 3b 20 05 <unknown>
mov z0.d, z0.d
// CHECK-INST: mov z0.d, z0.d
// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 30 60 04 <unknown>
mov z31.d, z0.d
// CHECK-INST: mov z31.d, z0.d
// CHECK-ENCODING: [0x1f,0x30,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 30 60 04 <unknown>
mov z5.b, #-128 mov z5.b, #-128
// CHECK-INST: mov z5.b, #-128 // CHECK-INST: mov z5.b, #-128
// CHECK-ENCODING: [0x05,0xd0,0x38,0x25] // CHECK-ENCODING: [0x05,0xd0,0x38,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 05 d0 38 25 <unknown> // CHECK-UNKNOWN: 05 d0 38 25 <unknown>
mov z5.b, #127 mov z5.b, #127
// CHECK-INST: mov z5.b, #127 // CHECK-INST: mov z5.b, #127
▲ Show 20 Lines • Show All 117 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate not compatible with encode/decode function.
orn z5.b, z5.b, #0xfa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.b, z5.b, #0xfa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z5.b, z5.b, #0xfff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.b, z5.b, #0xfff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z5.h, z5.h, #0xfffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.h, z5.h, #0xfffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z5.h, z5.h, #0xfffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z5.s, z5.s, #0xfffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z5.s, z5.s, #0xffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z15.d, z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
orn z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: orn z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orn z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: orn z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/orn.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
orn z5.b, z5.b, #0xf9
// CHECK-INST: orr z5.b, z5.b, #0x6
// CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
orn z23.h, z23.h, #0xfff9
// CHECK-INST: orr z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
orn z0.s, z0.s, #0xfffffff9
// CHECK-INST: orr z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
orn z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: orr z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
orn z5.b, z5.b, #0x6
// CHECK-INST: orr z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
orn z23.h, z23.h, #0x6
// CHECK-INST: orr z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
orn z0.s, z0.s, #0x6
// CHECK-INST: orr z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
orn z0.d, z0.d, #0x6
// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 03 05 <unknown>

llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate not compatible with encode/decode function.
orr z5.b, z5.b, #0xfa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.b, z5.b, #0xfa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z5.b, z5.b, #0xfff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.b, z5.b, #0xfff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z5.h, z5.h, #0xfffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.h, z5.h, #0xfffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z5.h, z5.h, #0xfffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.h, z5.h, #0xfffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z5.s, z5.s, #0xfffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.s, z5.s, #0xfffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z5.s, z5.s, #0xffffffffffffff9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z5.s, z5.s, #0xffffffffffffff9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z15.d, z15.d, #0xfffffffffffffffa
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
// CHECK-NEXT: orr z15.d, z15.d, #0xfffffffffffffffa
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
orr z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: orr z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orr z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: orr z0.d, p0/m, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
orr z21.d, z5.d, z26.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: orr z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate out of restricted predicate range
orr z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/orr.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
orr z5.b, z5.b, #0xf9
// CHECK-INST: orr z5.b, z5.b, #0xf9
// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
orr z23.h, z23.h, #0xfff9
// CHECK-INST: orr z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
orr z0.s, z0.s, #0xfffffff9
// CHECK-INST: orr z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
orr z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
orr z5.b, z5.b, #0x6
// CHECK-INST: orr z5.b, z5.b, #0x6
// CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
orr z23.h, z23.h, #0x6
// CHECK-INST: orr z23.h, z23.h, #0x6
// CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
orr z0.s, z0.s, #0x6
// CHECK-INST: orr z0.s, z0.s, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
orr z0.d, z0.d, #0x6
// CHECK-INST: orr z0.d, z0.d, #0x6
// CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
orr z0.d, z0.d, z0.d // should use mov-alias
// CHECK-INST: mov z0.d, z0.d
// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 30 60 04 <unknown>
orr z23.d, z13.d, z8.d // should not use mov-alias
// CHECK-INST: orr z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 31 68 04 <unknown>
orr z31.b, p7/m, z31.b, z31.b
// CHECK-INST: orr z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x18,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 18 04 <unknown>
orr z31.h, p7/m, z31.h, z31.h
// CHECK-INST: orr z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x58,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 58 04 <unknown>
orr z31.s, p7/m, z31.s, z31.s
// CHECK-INST: orr z31.s, p7/m, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0x98,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 98 04 <unknown>
orr z31.d, p7/m, z31.d, z31.d
// CHECK-INST: orr z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f d8 04 <unknown>