This is an archive of the discontinued LLVM Phabricator instance.

[AArch64][SVE] Asm: Support for ADD (immediate) instructions.
ClosedPublic

Authored by sdesmalen on May 24 2018, 12:14 AM.

Details

Summary

This patch adds addsub_imm8_opt_lsl_(i8|i16|i32|i64) operands
that are unsigned values in the range 0 to 255. For element widths of
16 bits or higher it may also be a signed multiple of 256 in the
range 0 to 65280.

Note: This also does some refactoring to reuse convenience function
getShiftedVal<shift>(), and now allows AArch64 scalar 'ADD #-4096' to be
accepted to be mapped to SUB #4096.

Diff Detail

Event Timeline

sdesmalen created this revision.May 24 2018, 12:14 AM
sdesmalen updated this revision to Diff 148371.May 24 2018, 3:59 AM
  • Removed some brackets and updated the patch to reflect change in D47309.
javed.absar added inline comments.May 24 2018, 12:04 PM
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
710

nitpick. ':' not needed

lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
783

nitpick : maybe factor out

bool Is8Bit = (uint8_t(Imm) == Imm);

sdesmalen updated this revision to Diff 148571.May 25 2018, 3:03 AM

Addressed nits and cleanup isSVEAddSubImm.

sdesmalen marked 2 inline comments as done.May 25 2018, 3:04 AM
fhahn added inline comments.May 25 2018, 3:31 AM
test/MC/AArch64/basic-a64-diagnostics.s
79

Why did this change?

fhahn accepted this revision.May 25 2018, 4:09 AM

LGTM.

test/MC/AArch64/basic-a64-diagnostics.s
79

Ah it's in the commit message.

This revision is now accepted and ready to land.May 25 2018, 4:09 AM
This revision was automatically updated to reflect the committed changes.