[AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.

[fhahn]

LGTM, thanks

lib/Target/AArch64/SVEInstrFormats.td

751

unrelated change

lib/Target/AArch64/AArch64InstrFormats.td

def uimm5s4 : Operand<i64>, ImmLeaf<i64,
   let PrintMethod = "printImmScale<4>";
 }
 def uimm5s8 : Operand<i64>, ImmLeaf<i64,
                 [{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }]> {
   let ParserMatchClass = UImm5s8Operand;
   let PrintMethod = "printImmScale<8>";
 }
 
+// uimm6sN predicate - True if the immediate is a multiple of N in the range
+// [0 * N, 64 * N].
+def UImm6s1Operand : UImmScaledMemoryIndexed<6, 1>;
+def UImm6s2Operand : UImmScaledMemoryIndexed<6, 2>;
+def UImm6s4Operand : UImmScaledMemoryIndexed<6, 4>;
+def UImm6s8Operand : UImmScaledMemoryIndexed<6, 8>;
+
+def uimm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
+  let ParserMatchClass = UImm6s1Operand;
+}
+def uimm6s2 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); }]> {
+  let PrintMethod = "printImmScale<2>";
+  let ParserMatchClass = UImm6s2Operand;
+}
+def uimm6s4 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); }]> {
+  let PrintMethod = "printImmScale<4>";
+  let ParserMatchClass = UImm6s4Operand;
+}
+def uimm6s8 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); }]> {
+  let PrintMethod = "printImmScale<8>";
+  let ParserMatchClass = UImm6s8Operand;
+}
+
 // simm4sN predicate - True if the immediate is a multiple of N in the range
 // [ -8* N, 7 * N].
 def SImm4s1Operand  : SImmScaledMemoryIndexed<4, 1>;
 def SImm4s2Operand  : SImmScaledMemoryIndexed<4, 2>;
 def SImm4s3Operand  : SImmScaledMemoryIndexed<4, 3>;
 def SImm4s4Operand  : SImmScaledMemoryIndexed<4, 4>;
 def SImm4s16Operand : SImmScaledMemoryIndexed<4, 16>;
 

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
   defm LD1W_IMM    : sve_mem_cld_si<0b1010, "ld1w",  Z_s, ZPR32>;
   defm LD1W_D_IMM  : sve_mem_cld_si<0b1011, "ld1w",  Z_d, ZPR64>;
   defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
   defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
   defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
   defm LD1D_IMM    : sve_mem_cld_si<0b1111, "ld1d",  Z_d, ZPR64>;
 
+  // LD1R loads (splat scalar to vector)
+  defm LD1RB_IMM    : sve_mem_ld_dup<0b00, 0b00, "ld1rb",  Z_b, ZPR8,  uimm6s1>;
+  defm LD1RB_H_IMM  : sve_mem_ld_dup<0b00, 0b01, "ld1rb",  Z_h, ZPR16, uimm6s1>;
+  defm LD1RB_S_IMM  : sve_mem_ld_dup<0b00, 0b10, "ld1rb",  Z_s, ZPR32, uimm6s1>;
+  defm LD1RB_D_IMM  : sve_mem_ld_dup<0b00, 0b11, "ld1rb",  Z_d, ZPR64, uimm6s1>;
+  defm LD1RSW_IMM   : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>;
+  defm LD1RH_IMM    : sve_mem_ld_dup<0b01, 0b01, "ld1rh",  Z_h, ZPR16, uimm6s2>;
+  defm LD1RH_S_IMM  : sve_mem_ld_dup<0b01, 0b10, "ld1rh",  Z_s, ZPR32, uimm6s2>;
+  defm LD1RH_D_IMM  : sve_mem_ld_dup<0b01, 0b11, "ld1rh",  Z_d, ZPR64, uimm6s2>;
+  defm LD1RSH_D_IMM : sve_mem_ld_dup<0b10, 0b00, "ld1rsh", Z_d, ZPR64, uimm6s2>;
+  defm LD1RSH_S_IMM : sve_mem_ld_dup<0b10, 0b01, "ld1rsh", Z_s, ZPR32, uimm6s2>;
+  defm LD1RW_IMM    : sve_mem_ld_dup<0b10, 0b10, "ld1rw",  Z_s, ZPR32, uimm6s4>;
+  defm LD1RW_D_IMM  : sve_mem_ld_dup<0b10, 0b11, "ld1rw",  Z_d, ZPR64, uimm6s4>;
+  defm LD1RSB_D_IMM : sve_mem_ld_dup<0b11, 0b00, "ld1rsb", Z_d, ZPR64, uimm6s1>;
+  defm LD1RSB_S_IMM : sve_mem_ld_dup<0b11, 0b01, "ld1rsb", Z_s, ZPR32, uimm6s1>;
+  defm LD1RSB_H_IMM : sve_mem_ld_dup<0b11, 0b10, "ld1rsb", Z_h, ZPR16, uimm6s1>;
+  defm LD1RD_IMM    : sve_mem_ld_dup<0b11, 0b11, "ld1rd",  Z_d, ZPR64, uimm6s8>;
+
+  // LD1RQ loads (load quadword-vector and splat to scalable vector)
   defm LD1RQ_B_IMM  : sve_mem_ldqr_si<0b00, "ld1rqb", Z_b, ZPR8>;
   defm LD1RQ_H_IMM  : sve_mem_ldqr_si<0b01, "ld1rqh", Z_h, ZPR16>;
   defm LD1RQ_W_IMM  : sve_mem_ldqr_si<0b10, "ld1rqw", Z_s, ZPR32>;
   defm LD1RQ_D_IMM  : sve_mem_ldqr_si<0b11, "ld1rqd", Z_d, ZPR64>;
   defm LD1RQ_B      : sve_mem_ldqr_ss<0b00, "ld1rqb", Z_b, ZPR8,  GPR64NoXZRshifted8>;
   defm LD1RQ_H      : sve_mem_ldqr_ss<0b01, "ld1rqh", Z_h, ZPR16, GPR64NoXZRshifted16>;
   defm LD1RQ_W      : sve_mem_ldqr_ss<0b10, "ld1rqw", Z_s, ZPR32, GPR64NoXZRshifted32>;
   defm LD1RQ_D      : sve_mem_ldqr_ss<0b11, "ld1rqd", Z_d, ZPR64, GPR64NoXZRshifted64>;

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidMemoryIndexed16SImm7:
     return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008].");
   case Match_InvalidMemoryIndexed8UImm5:
     return Error(Loc, "index must be a multiple of 8 in range [0, 248].");
   case Match_InvalidMemoryIndexed4UImm5:
     return Error(Loc, "index must be a multiple of 4 in range [0, 124].");
   case Match_InvalidMemoryIndexed2UImm5:
     return Error(Loc, "index must be a multiple of 2 in range [0, 62].");
+  case Match_InvalidMemoryIndexed8UImm6:
+    return Error(Loc, "index must be a multiple of 8 in range [0, 504].");
+  case Match_InvalidMemoryIndexed4UImm6:
+    return Error(Loc, "index must be a multiple of 4 in range [0, 252].");
+  case Match_InvalidMemoryIndexed2UImm6:
+    return Error(Loc, "index must be a multiple of 2 in range [0, 126].");
+  case Match_InvalidMemoryIndexed1UImm6:
+    return Error(Loc, "index must be in range [0, 63].");
   case Match_InvalidMemoryWExtend8:
     return Error(Loc,
                  "expected 'uxtw' or 'sxtw' with optional shift of #0");
   case Match_InvalidMemoryWExtend16:
     return Error(Loc,
                  "expected 'uxtw' or 'sxtw' with optional shift of #0 or #1");
   case Match_InvalidMemoryWExtend32:
     return Error(Loc,
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMemoryIndexed4SImm4:
   case Match_InvalidMemoryIndexed16SImm4:
   case Match_InvalidMemoryIndexed4SImm7:
   case Match_InvalidMemoryIndexed8SImm7:
   case Match_InvalidMemoryIndexed16SImm7:
   case Match_InvalidMemoryIndexed8UImm5:
   case Match_InvalidMemoryIndexed4UImm5:
   case Match_InvalidMemoryIndexed2UImm5:
+  case Match_InvalidMemoryIndexed1UImm6:
+  case Match_InvalidMemoryIndexed2UImm6:
+  case Match_InvalidMemoryIndexed4UImm6:
+  case Match_InvalidMemoryIndexed8UImm6:
   case Match_InvalidMemoryIndexedSImm6:
   case Match_InvalidMemoryIndexedSImm5:
   case Match_InvalidMemoryIndexedSImm9:
   case Match_InvalidMemoryIndexed8SImm10:
   case Match_InvalidImm0_1:
   case Match_InvalidImm0_7:
   case Match_InvalidImm0_15:
   case Match_InvalidImm0_31:

lib/Target/AArch64/SVEInstrFormats.td

 
 multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
   def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
   def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
   def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
   def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
 }
 
+
 //===----------------------------------------------------------------------===//
 // SVE Memory - Contiguous Load Group
 //===----------------------------------------------------------------------===//
 
 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
                           RegisterOperand VecList>
 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",

 multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty,
                            ZPRRegOp zprty, RegisterOperand gprty> {
   def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
                   (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
+class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
+                     RegisterOperand VecList, Operand immtype>
+: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
+  asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zt;
+  bits<6> imm6;
+  let Inst{31-25} = 0b1000010;
+  let Inst{24-23} = dtypeh;
+  let Inst{22}    = 1;
+  let Inst{21-16} = imm6;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = dtypel;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+}
+
+multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
+                          RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> {
+  def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+                  (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+}
+
 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
                           RegisterOperand VecList>
 : I<(outs VecList:$Zt), iops,
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
   def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
                   (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
                   (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
-}
+}
 

test/MC/AArch64/SVE/ld1rb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [0, 63].
+
+ld1rb z0.b, p1/z, [x0, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
+// CHECK-NEXT: ld1rb z0.b, p1/z, [x0, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rb z0.b, p1/z, [x0, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
+// CHECK-NEXT: ld1rb z0.b, p1/z, [x0, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rb z0.b, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rb z0.b, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rb   { z0.b }, p0/z, [x0]
+// CHECK-INST: ld1rb   { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 40 84 <unknown>
+
+ld1rb   { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1rb   { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 84 <unknown>
+
+ld1rb   { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1rb   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 40 84 <unknown>
+
+ld1rb   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rb   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 40 84 <unknown>
+
+ld1rb   { z31.b }, p7/z, [sp, #63]
+// CHECK-INST: ld1rb   { z31.b }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0x9f,0x7f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 7f 84 <unknown>
+
+ld1rb   { z31.h }, p7/z, [sp, #63]
+// CHECK-INST: ld1rb   { z31.h }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0xbf,0x7f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 7f 84 <unknown>
+
+ld1rb   { z31.s }, p7/z, [sp, #63]
+// CHECK-INST: ld1rb   { z31.s }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0xdf,0x7f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 7f 84 <unknown>
+
+ld1rb   { z31.d }, p7/z, [sp, #63]
+// CHECK-INST: ld1rb   { z31.d }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0xff,0x7f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 7f 84 <unknown>

test/MC/AArch64/SVE/ld1rd-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (multiple of 4 in range [0, 252]).
+
+ld1rd z0.d, p1/z, [x0, #-8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
+// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #-8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.d, p1/z, [x0, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
+// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.d, p1/z, [x0, #505]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
+// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #505]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.d, p1/z, [x0, #512]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
+// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #512]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.d, p1/z, [x0, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
+// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rd z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rd z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.h, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rd z0.h, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rd z0.s, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rd z0.d, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rd z0.d, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rd.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rd   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rd   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 c0 85 <unknown>
+
+ld1rd   { z31.d }, p7/z, [sp, #504]
+// CHECK-INST: ld1rd   { z31.d }, p7/z, [sp, #504]
+// CHECK-ENCODING: [0xff,0xff,0xff,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff ff 85 <unknown>

test/MC/AArch64/SVE/ld1rh-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (multiple of 2 in range [0, 126]).
+
+ld1rh z0.h, p1/z, [x0, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rh z0.h, p1/z, [x0, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rh z0.h, p1/z, [x0, #127]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #127]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rh z0.h, p1/z, [x0, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rh z0.h, p1/z, [x0, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rh z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rh z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rh z0.h, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rh z0.h, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rh.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rh   { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1rh   { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 84 <unknown>
+
+ld1rh   { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1rh   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 c0 84 <unknown>
+
+ld1rh   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rh   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 c0 84 <unknown>
+
+ld1rh   { z31.h }, p7/z, [sp, #126]
+// CHECK-INST: ld1rh   { z31.h }, p7/z, [sp, #126]
+// CHECK-ENCODING: [0xff,0xbf,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ff 84 <unknown>
+
+ld1rh   { z31.s }, p7/z, [sp, #126]
+// CHECK-INST: ld1rh   { z31.s }, p7/z, [sp, #126]
+// CHECK-ENCODING: [0xff,0xdf,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df ff 84 <unknown>
+
+ld1rh   { z31.d }, p7/z, [sp, #126]
+// CHECK-INST: ld1rh   { z31.d }, p7/z, [sp, #126]
+// CHECK-ENCODING: [0xff,0xff,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff ff 84 <unknown>

test/MC/AArch64/SVE/ld1rsb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (in range [0, 63]).
+
+ld1rsb z0.h, p1/z, [x0, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
+// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsb z0.h, p1/z, [x0, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
+// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rsb z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rsb z0.h, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rsb  { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1rsb  { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0xc0,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 c0 85 <unknown>
+
+ld1rsb  { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1rsb  { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 85 <unknown>
+
+ld1rsb  { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rsb  { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 c0 85 <unknown>
+
+ld1rsb  { z31.h }, p7/z, [sp, #63]
+// CHECK-INST: ld1rsb  { z31.h }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0xdf,0xff,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df ff 85 <unknown>
+
+ld1rsb  { z31.s }, p7/z, [sp, #63]
+// CHECK-INST: ld1rsb  { z31.s }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0xbf,0xff,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ff 85 <unknown>
+
+ld1rsb  { z31.d }, p7/z, [sp, #63]
+// CHECK-INST: ld1rsb  { z31.d }, p7/z, [sp, #63]
+// CHECK-ENCODING: [0xff,0x9f,0xff,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f ff 85 <unknown>

test/MC/AArch64/SVE/ld1rsh-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (multiple of 2 in range [0, 126]).
+
+ld1rsh z0.s, p1/z, [x0, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rsh z0.s, p1/z, [x0, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsh z0.s, p1/z, [x0, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rsh z0.s, p1/z, [x0, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsh z0.s, p1/z, [x0, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 126].
+// CHECK-NEXT: ld1rsh z0.s, p1/z, [x0, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rsh z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsh z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsh z0.h, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsh z0.h, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rsh z0.s, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rsh z0.s, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsh.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rsh  { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1rsh  { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 85 <unknown>
+
+ld1rsh  { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rsh  { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 40 85 <unknown>
+
+ld1rsh  { z31.s }, p7/z, [sp, #126]
+// CHECK-INST: ld1rsh  { z31.s }, p7/z, [sp, #126]
+// CHECK-ENCODING: [0xff,0xbf,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 7f 85 <unknown>
+
+ld1rsh  { z31.d }, p7/z, [sp, #126]
+// CHECK-INST: ld1rsh  { z31.d }, p7/z, [sp, #126]
+// CHECK-ENCODING: [0xff,0x9f,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 7f 85 <unknown>

test/MC/AArch64/SVE/ld1rsw-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (multiple of 4 in range [0, 252]).
+
+ld1rsw z0.d, p1/z, [x0, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rsw z0.d, p1/z, [x0, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsw z0.d, p1/z, [x0, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rsw z0.d, p1/z, [x0, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsw z0.d, p1/z, [x0, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rsw z0.d, p1/z, [x0, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rsw z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsw z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsw z0.h, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsw z0.h, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rsw z0.s, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rsw z0.s, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rsw z0.d, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rsw z0.d, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rsw.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rsw  { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rsw  { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 c0 84 <unknown>
+
+ld1rsw  { z31.d }, p7/z, [sp, #252]
+// CHECK-INST: ld1rsw  { z31.d }, p7/z, [sp, #252]
+// CHECK-ENCODING: [0xff,0x9f,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f ff 84 <unknown>

test/MC/AArch64/SVE/ld1rw-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid immediate (multiple of 4 in range [0, 252]).
+
+ld1rw z0.s, p1/z, [x0, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rw z0.s, p1/z, [x0, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rw z0.s, p1/z, [x0, #253]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #253]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rw z0.s, p1/z, [x0, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rw z0.s, p1/z, [x0, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 252].
+// CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid result vector element size
+
+ld1rw z0.b, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rw z0.b, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1rw z0.h, p1/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1rw z0.h, p1/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1rw z0.s, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1rw z0.s, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1rw.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1rw   { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1rw   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 40 85 <unknown>
+
+ld1rw   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1rw   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 40 85 <unknown>
+
+ld1rw   { z31.s }, p7/z, [sp, #252]
+// CHECK-INST: ld1rw   { z31.s }, p7/z, [sp, #252]
+// CHECK-ENCODING: [0xff,0xdf,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 7f 85 <unknown>
+
+ld1rw   { z31.d }, p7/z, [sp, #252]
+// CHECK-INST: ld1rw   { z31.d }, p7/z, [sp, #252]
+// CHECK-ENCODING: [0xff,0xff,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 7f 85 <unknown>