[AArch64][SVE] Asm: Improve diagnostics for gather loads.

[sdesmalen]

Summary

This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:

ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
                                 ^ 
         shift amount should be '1'

Instead of suggesting the packed, unscaled addressing mode:

expected 'z[0..31].d, (uxtw|sxtw)'

the assembler now suggests using the proper scaling:

expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'

[fhahn]

LGTM thanks

lib/Target/AArch64/AArch64RegisterInfo.td

 def ZZZZ_s : RegisterOperand<ZPR4, "printTypedVectorList<0,'s'>"> {
   let ParserMatchClass = ZPRVectorList<32, 4>;
 }
 
 def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
   let ParserMatchClass = ZPRVectorList<64, 4>;
 }
 
-class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale>
-    : AsmOperandClass {
-  let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale;
+class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
+                          bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
+  let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
+                         # !if(ScaleAlwaysSame, "Only", "");
+
   let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
                           # RegWidth # ", AArch64::ZPRRegClassID, "
                           # "AArch64_AM::" # ShiftExtend # ", "
-                          # Scale # ">";
+                          # Scale # ", "
+                          # !if(ScaleAlwaysSame, "true", "false")
+                          # ">";
   let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
   let RenderMethod = "addRegOperands";
   let ParserMethod = "tryParseSVEDataVector<true, true>";
 }
 
 class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,
-                               int RegWidth, int Scale> : RegisterOperand<ZPR> {
+                               int RegWidth, int Scale, string Suffix = "">
+    : RegisterOperand<ZPR> {
   let ParserMatchClass =
-    !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale);
+    !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
   let PrintMethod = "printRegWithShiftExtend<"
                           # !if(SignExtend, "true", "false") # ", "
                           # Scale # ", "
                           # !if(IsLSL, "'x'", "'w'") # ", "
                           # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
 }
 
 foreach RegWidth = [32, 64] in {
   // UXTW(8|16|32|64)
+  def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
   def ZPR#RegWidth#AsmOpndExtUXTW8     : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
   def ZPR#RegWidth#AsmOpndExtUXTW16    : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
   def ZPR#RegWidth#AsmOpndExtUXTW32    : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
   def ZPR#RegWidth#AsmOpndExtUXTW64    : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
 
+  def ZPR#RegWidth#ExtUXTW8Only        : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">;
   def ZPR#RegWidth#ExtUXTW8            : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
   def ZPR#RegWidth#ExtUXTW16           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
   def ZPR#RegWidth#ExtUXTW32           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
   def ZPR#RegWidth#ExtUXTW64           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>;
 
   // SXTW(8|16|32|64)
+  def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;
   def ZPR#RegWidth#AsmOpndExtSXTW8     : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
   def ZPR#RegWidth#AsmOpndExtSXTW16    : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
   def ZPR#RegWidth#AsmOpndExtSXTW32    : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
   def ZPR#RegWidth#AsmOpndExtSXTW64    : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
 
+  def ZPR#RegWidth#ExtSXTW8Only        : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">;
   def ZPR#RegWidth#ExtSXTW8            : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
   def ZPR#RegWidth#ExtSXTW16           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
   def ZPR#RegWidth#ExtSXTW32           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
   def ZPR#RegWidth#ExtSXTW64           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>;
 }
 
 // LSL(8|16|32|64)
 def ZPR64AsmOpndExtLSL8      : ZPRExtendAsmOperand<"LSL", 64, 8>;
 def ZPR64AsmOpndExtLSL16     : ZPRExtendAsmOperand<"LSL", 64, 16>;
 def ZPR64AsmOpndExtLSL32     : ZPRExtendAsmOperand<"LSL", 64, 32>;
 def ZPR64AsmOpndExtLSL64     : ZPRExtendAsmOperand<"LSL", 64, 64>;
-
 def ZPR64ExtLSL8             : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 8>;
 def ZPR64ExtLSL16            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 16>;
 def ZPR64ExtLSL32            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 32>;
 def ZPR64ExtLSL64            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 64>;
 
 class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
   let Name = AsmOperandName # Scale;
   let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s,  "ld3w", simm4s3>;
   defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>;
   defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d,   "ld2d", simm4s2>;
   defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d,  "ld3d", simm4s3>;
   defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
 
   // Gathers using unscaled 32-bit offsets, e.g.
   //    ld1h z0.s, p0/z, [x0, z0.s, uxtw]
-  defm GLD1SB_S   : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
-  defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
-  defm GLD1B_S    : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
-  defm GLDFF1B_S  : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1SB_S   : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
+  defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
+  defm GLD1B_S    : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
+  defm GLDFF1B_S  : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
   defm GLD1SH_S   : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
   defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
   defm GLD1H_S    : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
   defm GLDFF1H_S  : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
   defm GLD1W      : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
   defm GLDFF1W    : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
 
   // Gathers using scaled 32-bit offsets, e.g.
let Predicates = [HasSVE] in {
   defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
   defm GLD1W_D    : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w",    ZPR64ExtLSL32>;
   defm GLDFF1W_D  : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w",  ZPR64ExtLSL32>;
   defm GLD1D      : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d",    ZPR64ExtLSL64>;
   defm GLDFF1D    : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d",  ZPR64ExtLSL64>;
 
   // Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
   //    ld1h z0.d, p0/z, [x0, z0.d, uxtw]
-  defm GLD1SB_D   : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
-  defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
-  defm GLD1B_D    : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
-  defm GLDFF1B_D  : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+  defm GLD1SB_D   : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
+  defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
+  defm GLD1B_D    : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
+  defm GLDFF1B_D  : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
   defm GLD1SH_D   : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLD1H_D    : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLDFF1H_D  : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLD1SW_D   : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw",   ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLD1W_D    : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w",    ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
   defm GLDFF1W_D  : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w",  ZPR64ExtSXTW8, ZPR64ExtUXTW8>;

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

public:
 
   template <int ElementWidth, unsigned Class>
   bool isSVEVectorRegOfWidth() const {
     return isSVEVectorReg<Class>() &&
            (ElementWidth == 0 || Reg.ElementWidth == ElementWidth);
   }
 
   template <int ElementWidth, unsigned Class,
-            AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth>
+            AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
+            bool ShiftWidthAlwaysSame>
   DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (isSVEVectorRegOfWidth<ElementWidth, Class>() &&
-        ShiftExtendTy == getShiftExtendType() &&
-        getShiftExtendAmount() == Log2_32(ShiftWidth / 8))
+    if (!isSVEVectorRegOfWidth<ElementWidth, Class>())
+      return DiagnosticPredicateTy::NearMatch;
+
+    // Give a more specific diagnostic when the user has explicitly typed in
+    // a shift-amount that does not match what is expected, but for which
+    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
+    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
+    if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW ||
+                        ShiftExtendTy == AArch64_AM::SXTW) &&
+        !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (MatchShift && ShiftExtendTy == getShiftExtendType())
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;
   }
 
   bool isGPR32as64() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
       AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);

test/MC/AArch64/SVE/ld1d-diagnostics.s

 // Invalid scalar + vector addressing modes
 
 ld1d z0.d, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

test/MC/AArch64/SVE/ld1h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1h z0.s, p0/z, [z0.s, #-2]

test/MC/AArch64/SVE/ld1sh-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1sh z0.s, p0/z, [z0.s, #-2]

test/MC/AArch64/SVE/ld1sw-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1sw z0.s, p0/z, [z0.s]

test/MC/AArch64/SVE/ld1w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1w z0.s, p0/z, [z0.s, #-4]

test/MC/AArch64/SVE/ldff1d-diagnostics.s

 // Invalid scalar + vector addressing modes
 
 ldff1d z0.d, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

test/MC/AArch64/SVE/ldff1h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1h z0.s, p0/z, [z0.s, #-2]

test/MC/AArch64/SVE/ldff1sh-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1sh z0.s, p0/z, [z0.s, #-2]

test/MC/AArch64/SVE/ldff1sw-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1sw z0.s, p0/z, [z0.s]

test/MC/AArch64/SVE/ldff1w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, z0.s, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, z0.s, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1w z0.s, p0/z, [z0.s, #-4]