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[AArch64][SVE] Asm: Improve diagnostics for gather loads.
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Authored by sdesmalen on Apr 26 2018, 7:56 AM.

Details

Summary

This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:

ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
                                 ^ 
         shift amount should be '1'

Instead of suggesting the packed, unscaled addressing mode:

expected 'z[0..31].d, (uxtw|sxtw)'

the assembler now suggests using the proper scaling:

expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'

Diff Detail

Event Timeline

sdesmalen created this revision.Apr 26 2018, 7:56 AM
fhahn accepted this revision.Apr 27 2018, 1:36 AM

LGTM thanks

This revision is now accepted and ready to land.Apr 27 2018, 1:36 AM
This revision was automatically updated to reflect the committed changes.