[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.

[fhahn]

LGTM, thanks

[samparker]

Hi Sander,

Sorry to be pain, but could you point to the document that describes this please? From the supplement, I can't see why a shifted operand is invalid.

cheers,
sam

[sdesmalen]

In D46121#1082480, @samparker wrote:

Sorry to be pain, but could you point to the document that describes this please? From the supplement, I can't see why a shifted operand is invalid.

Hi Sam, if you download the spec from:

https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

the SVE Supplement links to the SVE Instruction Index in section 5.2.1. This should open the xhtml/index.html page with a list of all the instructions and all their details. For some reason the PDF link doesn't work for me, so opening the index.html directly is probably easiest. (I think the specific file you're looking for is: st1b_z_p_br.html)

[samparker]

Thanks!

[samparker]

Ok, for my sanity, I don't think the document descriptions match up, do you agree? The useful link you pointed me to only shows Xm as the scalar index, but 5.2.2 of the PDF supplement shows that the index can be scaled with LSL.

[sdesmalen]

Are you referring to the 'assembler syntax' table? I think this table needs to be read in conjunction with the following paragraph (section 5.2.2, page 42):

Load, store, and prefetch instructions that multiply a scalar index register or an index vector element by the memory element access size specify a shift type, followed by a shift amount in bits. The shift type can be one of LSL, SXTW, or UXTW. The shift amount is always Log2 of the memory element access size, in bytes. The shift amount defaults to zero when the memory element access size is a byte. The shift type of LSL must be omitted if the shift amount is omitted.

[samparker]

Ah, thanks for clearing that up for me.

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
   defm ST1H_IMM   : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
   defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
   defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
   defm ST1W_IMM   : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>;
   defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
   defm ST1D_IMM   : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
 
+  // contiguous store with reg+reg addressing.
+  defm ST1B   : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8,  GPR64NoXZRshifted8>;
+  defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
+  defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
+  defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
+  defm ST1H   : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
+  defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
+  defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
+  defm ST1W   : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
+  defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
+  defm ST1D   : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
+
  // ST{2,3,4}{B,H,W,D} with immediate
   defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b,   "st2b", simm4Scale2MulVl>;
   defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b,  "st3b", simm4Scale3MulVl>;
   defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4Scale4MulVl>;
   defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h,   "st2h", simm4Scale2MulVl>;
   defm ST3H_IMM : sve_mem_est_si<0b01, 0b10, ZZZ_h,  "st3h", simm4Scale3MulVl>;
   defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4Scale4MulVl>;
   defm ST2W_IMM : sve_mem_est_si<0b10, 0b01, ZZ_s,   "st2w", simm4Scale2MulVl>;

lib/Target/AArch64/SVEInstrFormats.td

 multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                           string asm, Operand immtype> {
   def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
                   (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
+class sve_mem_cst_ss_base<bits<4> dtype, string asm,
+                          RegisterOperand listty, RegisterOperand gprty>
+: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+  asm, "\t$Zt, $Pg, [$Rn, $Rm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rm;
+  bits<5> Rn;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1110010;
+  let Inst{24-21} = dtype;
+  let Inst{20-16} = Rm;
+  let Inst{15-13} = 0b010;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayStore = 1;
+}
+
+multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
+                          RegisterOperand listty, ZPRRegOp zprty,
+                          RegisterOperand gprty> {
+  def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+}
+
 //===----------------------------------------------------------------------===//
 // SVE Permute - Predicates Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
                                PPRRegOp pprty>
 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
   asm, "\t$Pd, $Pn, $Pm",
multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
   def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
                   (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
                   (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
-}
+}
 

test/MC/AArch64/SVE/st1b-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b { z1.b, z2.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b { v0.16b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b { v0.16b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1b z0.b, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff 6f e4 <unknown>
 
 st1b    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1b    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 65 e4 <unknown>
+
+st1b    { z0.b }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.b }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 e4 <unknown>
+
+st1b    { z0.h }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.h }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x20,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 20 e4 <unknown>
+
+st1b    { z0.s }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.s }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e4 <unknown>
+
+st1b    { z0.d }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.d }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e4 <unknown>

test/MC/AArch64/SVE/st1d-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d { v0.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1d { v0.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1d z0.d, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff ef e5 <unknown>
 
 st1d    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1d    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 e5 e5 <unknown>
+
+st1d    { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e5 <unknown>

test/MC/AArch64/SVE/st1h-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h { z1.h, z2.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1h { v0.8h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h { v0.8h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1h z0.h, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 e5 e4 <unknown>
 
 st1h    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1h    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xef,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff ef e4 <unknown>
+
+st1h    { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xa0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 e4 <unknown>
+
+st1h    { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 e4 <unknown>
+
+st1h    { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e4 <unknown>

test/MC/AArch64/SVE/st1w-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w { z1.s, z2.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1w { v0.4s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w { v0.4s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1w z0.s, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/st1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff 6f e5 <unknown>
 
 st1w    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1w    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 65 e5 <unknown>
+
+st1w    { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e5 <unknown>
+
+st1w    { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e5 <unknown>