[MIPS GlobalISel] Add lowerCall

[Petar.Avramovic]

Summary

Add the minimal support to lower function calls.
Support only functions with arguments/return that go through registers, and have type i32.

[Petar.Avramovic]

Does anybody have any comment?

[dsanders]

I've only gone through the ABI side of things (and from memory) but I have a couple comments.

lib/Target/Mips/MipsCallLowering.cpp

279 ↗

(On Diff #142426)

I assume it's O32 you're implementing based on the magic number here. IIRC, there's a function in the Mips target that returns 0 or 16 as appropriate for the ABI. If it used that instead then I suspect this patch may support N32/N64 too.

test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll

6 ↗

(On Diff #142426)

I would suggest not using the first two arguments so that code is emitted to put the arguments in the right place. This test will currently emit the right assembly even if argument passing isn't handled. If you added two dummy arguments in front of these then there would be a mov instruction you can check for.

21 ↗

(On Diff #142426)

Similarly, I'd suggest modifying the result before passing it back to the caller so that code using $v0 is emitted. Then you'd be able to check the register is correct.

[sdardis]

lib/Target/Mips/MipsCallLowering.cpp

222 ↗

(On Diff #142426)

Fallback if we have more than 4 arguments, var-args or the calling convention is not supported.

224 ↗

(On Diff #142426)

Test that we have no 'byval' arguments here, they require some MIPS-specific special handling. See D44296 for the details on how to handle this, but note that clang doesn't currently produce function calls with 'byval'. 'sret' arguments should also provoke fallback as well.

236 ↗

(On Diff #142426)

FIXME: Add support for pic calling sequences, long call sequences for O32, N32 and N64.

279 ↗

(On Diff #142426)

The MipsABIInfo class knows the fixed portion of the outing argument area, GetCalleeAllocdArgSizeInBytes().

[Petar.Avramovic]

Addressed review comments

[Petar.Avramovic]

lib/Target/Mips/MipsCallLowering.cpp

222 ↗

(On Diff #142426)

Add fallback if calling convention is not the default one (CallingConv::C).
If we get more then 4 arguments fallback happens in MipsCallLowering::MipsHandler::assign (MipsCallLowering.cpp line 30) as those arguments will end up on stack.
As for var-arg functions, there is no work to be done in lowerCall. They are handled in lowerFormalArguments, we will have to copy argument from registers to stack (if any) and store address of startig location of var-args in MipsFunctionInfo object (using setVarArgsFrameIndex). Remaining work is done with custom legalization in legalizer.

236 ↗

(On Diff #142426)

Add FIXME comment pic and long call. And as we are adding this comment also add fallback if callee is not a symbol since we have to support callee in register (pointer to function) first.

279 ↗

(On Diff #142426)

When we add support for arguments on stack in lowerCall, GetCalleeAllocdArgSizeInBytes will be used to AllocateStack in MipsCCState so it can be used correctly. There is similar work to be done in lowerFormalArguments too.
In the meantime we will use ABI.GetCalleeAllocdArgSizeInBytes() instead of 16 in ADJCALLSTACK... instructions.

test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll

6 ↗

(On Diff #142426)

Tests are modified so that we can see move from a2,a3($6,$7) to a0,a1($4,$5) when we are preparing arguments for call of function f.

21 ↗

(On Diff #142426)

Return value of f is doubled in order to see if value in register v0($2) is used in add instruction.

[Petar.Avramovic]

Does anybody have any comment?

[Petar.Avramovic]

Ping

[Petar.Avramovic]

Ping

[sdardis]

LGTM.

llvm/trunk/lib/Target/Mips/MipsCallLowering.h

public:
   MipsCallLowering(const MipsTargetLowering &TLI);
 
   bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
                    unsigned VReg) const override;
 
   bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
                             ArrayRef<unsigned> VRegs) const override;
 
+  bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
+                 const MachineOperand &Callee, const ArgInfo &OrigRet,
+                 ArrayRef<ArgInfo> OrigArgs) const override;
+
 private:
   using FunTy =
       std::function<void(ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
                          unsigned origIdx, unsigned partOffs)>;
 
   /// Based on registers available on target machine split or extend
   /// type if needed, also change pointer type to appropriate integer
   /// type. Lambda will fill some info so we can tell MipsCCState to

llvm/trunk/lib/Target/Mips/MipsCallLowering.cpp

 /// \file
 /// This file implements the lowering of LLVM calls to machine code calls for
 /// GlobalISel.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsCallLowering.h"
 #include "MipsCCState.h"
+#include "MipsTargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 
 using namespace llvm;
 
 MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
 bool MipsCallLowering::MipsHandler::assign(const CCValAssign &VA,
IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
       : MipsHandler(MIRBuilder, MRI) {}
 
   bool handle(ArrayRef<CCValAssign> ArgLocs,
               ArrayRef<CallLowering::ArgInfo> Args);
 
 private:
   virtual void assignValueToReg(unsigned ValVReg, unsigned PhysReg) override;
 
-  void markPhysRegUsed(unsigned PhysReg) {
+  virtual void markPhysRegUsed(unsigned PhysReg) {
     MIRBuilder.getMBB().addLiveIn(PhysReg);
   }
 };
+
+class CallReturnHandler : public IncomingValueHandler {
+public:
+  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+                    MachineInstrBuilder &MIB)
+      : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
+
+private:
+  virtual void markPhysRegUsed(unsigned PhysReg) override {
+    MIB.addDef(PhysReg, RegState::Implicit);
+  }
+
+  MachineInstrBuilder &MIB;
+};
+
 } // end anonymous namespace
 
 void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
                                             unsigned PhysReg) {
   MIRBuilder.buildCopy(ValVReg, PhysReg);
   markPhysRegUsed(PhysReg);
 }
 
bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
 
   IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
   if (!Handler.handle(ArgLocs, ArgInfos))
     return false;
 
   return true;
 }
 
+bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
+                                 CallingConv::ID CallConv,
+                                 const MachineOperand &Callee,
+                                 const ArgInfo &OrigRet,
+                                 ArrayRef<ArgInfo> OrigArgs) const {
+
+  if (CallConv != CallingConv::C)
+    return false;
+
+  for (auto &Arg : OrigArgs) {
+    if (!isSupportedType(Arg.Ty))
+      return false;
+    if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
+      return false;
+  }
+  if (OrigRet.Reg && !isSupportedType(OrigRet.Ty))
+    return false;
+
+  MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
+  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
+  const MipsTargetMachine &TM =
+      static_cast<const MipsTargetMachine &>(MF.getTarget());
+  const MipsABIInfo &ABI = TM.getABI();
+
+  MachineInstrBuilder CallSeqStart =
+      MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
+
+  // FIXME: Add support for pic calling sequences, long call sequences for O32,
+  //       N32 and N64. First handle the case when Callee.isReg().
+  if (Callee.isReg())
+    return false;
+
+  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
+  MIB.addDef(Mips::SP, RegState::Implicit);
+  MIB.add(Callee);
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
+
+  TargetLowering::ArgListTy FuncOrigArgs;
+  FuncOrigArgs.reserve(OrigArgs.size());
+
+  SmallVector<ArgInfo, 8> ArgInfos;
+  SmallVector<unsigned, 8> OrigArgIndices;
+  unsigned i = 0;
+  for (auto &Arg : OrigArgs) {
+
+    TargetLowering::ArgListEntry Entry;
+    Entry.Ty = Arg.Ty;
+    FuncOrigArgs.push_back(Entry);
+
+    splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
+    ++i;
+  }
+
+  SmallVector<ISD::OutputArg, 8> Outs;
+  subTargetRegTypeForCallingConv(
+      MIRBuilder, ArgInfos, OrigArgIndices,
+      [&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used, unsigned origIdx,
+          unsigned partOffs) {
+        Outs.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
+      });
+
+  SmallVector<CCValAssign, 8> ArgLocs;
+  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
+                     F.getContext());
+
+  const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
+  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
+
+  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
+  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
+    return false;
+  }
+
+  // TODO: Calculate stack offset.
+  CallSeqStart.addImm(ABI.GetCalleeAllocdArgSizeInBytes(CallConv)).addImm(0);
+  MIRBuilder.insertInstr(MIB);
+
+  if (OrigRet.Reg) {
+
+    ArgInfos.clear();
+    SmallVector<unsigned, 8> OrigRetIndices;
+
+    splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
+
+    SmallVector<ISD::InputArg, 8> Ins;
+    subTargetRegTypeForCallingConv(
+        MIRBuilder, ArgInfos, OrigRetIndices,
+        [&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
+            unsigned origIdx, unsigned partOffs) {
+          Ins.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
+        });
+
+    SmallVector<CCValAssign, 8> ArgLocs;
+    MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
+                       F.getContext());
+
+    CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
+
+    CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
+    if (!Handler.handle(ArgLocs, ArgInfos))
+      return false;
+  }
+
+  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP)
+      .addImm(ABI.GetCalleeAllocdArgSizeInBytes(CallConv))
+      .addImm(0);
+
+  return true;
+}
+
 void MipsCallLowering::subTargetRegTypeForCallingConv(
     MachineIRBuilder &MIRBuilder, ArrayRef<ArgInfo> Args,
     ArrayRef<unsigned> OrigArgIndices, const FunTy &PushBack) const {
   MachineFunction &MF = MIRBuilder.getMF();
   const Function &F = MF.getFunction();
   const DataLayout &DL = F.getParent()->getDataLayout();
   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
 

llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+declare i32 @f(i32 %a, i32 %b);
+
+define i32 @g(i32 %a0, i32 %a1, i32 %x, i32 %y) {
+  ; MIPS32-LABEL: name: g
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+  ; MIPS32:   ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+  ; MIPS32:   $a0 = COPY [[COPY2]](s32)
+  ; MIPS32:   $a1 = COPY [[COPY3]](s32)
+  ; MIPS32:   JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+  ; MIPS32:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+  ; MIPS32:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
+  ; MIPS32:   $v0 = COPY [[ADD]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %z = call i32 @f(i32 %x, i32 %y)
+  %doublez = add i32 %z, %z
+  ret i32 %doublez
+}

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+declare i32 @f(i32 %a, i32 %b);
+
+define i32 @g(i32 %a0, i32 %a1, i32 %x, i32 %y) {
+; MIPS32-LABEL: g:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    move $4, $6
+; MIPS32-NEXT:    move $5, $7
+; MIPS32-NEXT:    jal f
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    addu $2, $2, $2
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %z = call i32 @f(i32 %x, i32 %y)
+  %doublez = add i32 %z, %z
+  ret i32 %doublez
+}