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Differential D45313

[AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
ClosedPublic

Authored by dp on Apr 5 2018, 2:39 AM.

Details

Reviewers
arsenm
artem.tamazov
timcorringham
Commits
rG306b1a0119e6: [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
rL329430: [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
Summary

See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844

Diff Detail

Event Timeline

dp created this revision.Apr 5 2018, 2:39 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptApr 5 2018, 2:39 AM
arsenm accepted this revision.Apr 5 2018, 7:39 AM

LGTM

This revision is now accepted and ready to land.Apr 5 2018, 7:39 AM
artem.tamazov accepted this revision.Apr 5 2018, 8:54 AM

Looks good.

Closed by commit rL329430: [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done (authored by dpreobra). · Explain WhyApr 6 2018, 10:27 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 6 2018, 10:27 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
7 lines
test/
MC/
AMDGPU/
15 lines
Disassembler/
AMDGPU/
4 lines

Diff 141117

lib/Target/AMDGPU/SOPInstructions.td

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let SubtargetPredicate = isVI in { let SubtargetPredicate = isVI in {
def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> { def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
let simm16 = 0; let simm16 = 0;
let isBarrier = 1; let isBarrier = 1;
let isReturn = 1; let isReturn = 1;
} }
} }
let SubtargetPredicate = isGFX9 in {
let isBarrier = 1, isReturn = 1, simm16 = 0 in {
def S_ENDPGM_ORDERED_PS_DONE :
SOPP<0x01e, (ins), "s_endpgm_ordered_ps_done">;
} // End isBarrier = 1, isReturn = 1, simm16 = 0
} // End SubtargetPredicate = isGFX9
let isBranch = 1, SchedRW = [WriteBranch] in { let isBranch = 1, SchedRW = [WriteBranch] in {
def S_BRANCH : SOPP < def S_BRANCH : SOPP <
0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
[(br bb:$simm16)]> { [(br bb:$simm16)]> {
let isBarrier = 1; let isBarrier = 1;
} }
let Uses = [SCC] in { let Uses = [SCC] in {
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test/MC/AMDGPU/sopk.s

// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOSI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOVI %s
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
s_movk_i32 s2, 0x6 s_movk_i32 s2, 0x6
// GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0] // GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
s_cmovk_i32 s2, 0x6 s_cmovk_i32 s2, 0x6
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s_setreg_imm32_b32 0x6, 0xff s_setreg_imm32_b32 0x6, 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] // SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] // VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
// HW register identifier, non-default offset/width // HW register identifier, non-default offset/width
s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00] // SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00] // VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
s_endpgm_ordered_ps_done
// GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
// NOSICIVI: error: instruction not supported on this GPU

test/MC/Disassembler/AMDGPU/sopk_gfx9.txt

  • This file was added.
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
0x00,0x00,0x9e,0xbf