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Differential D45268

[AMDGPU][MC][GFX9] Added s_call_b64
ClosedPublic

Authored by dp on Apr 4 2018, 10:30 AM.

Details

Reviewers
arsenm
artem.tamazov
timcorringham
Commits
rGae31223ba715: [AMDGPU][MC][GFX9] Added s_call_b64
rL329440: [AMDGPU][MC][GFX9] Added s_call_b64
Summary

See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843

I had to correct a lit test data.s because seemingly unused combination of bits

.long 0xbadc0de1

turned out to be a valid gfx9 instruction:

s_call_b64 s[92:93], 0xde1

Isn't it curious?

Diff Detail

Event Timeline

dp created this revision.Apr 4 2018, 10:30 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptApr 4 2018, 10:30 AM
artem.tamazov accepted this revision.Apr 5 2018, 8:53 AM

LGTM

This revision is now accepted and ready to land.Apr 5 2018, 8:53 AM
Closed by commit rL329440: [AMDGPU][MC][GFX9] Added s_call_b64 (authored by dpreobra). · Explain WhyApr 6 2018, 11:27 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 6 2018, 11:27 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
11 lines
test/
MC/
AMDGPU/
24 lines
23 lines
Disassembler/
AMDGPU/
11 lines

Diff 140987

lib/Target/AMDGPU/SOPInstructions.td

Show First 20 Lines • Show All 655 Lines • ▼ Show 20 Linesdef S_SETREG_IMM32_B32 : SOPK_Pseudo <
(outs), (ins i32imm:$imm, hwreg:$simm16), (outs), (ins i32imm:$imm, hwreg:$simm16),
"$simm16, $imm"> { "$simm16, $imm"> {
let Size = 8; // Unlike every other SOPK instruction. let Size = 8; // Unlike every other SOPK instruction.
let has_sdst = 0; let has_sdst = 0;
} }
} // End hasSideEffects = 1 } // End hasSideEffects = 1
let SubtargetPredicate = isGFX9 in {
def S_CALL_B64 : SOPK_Pseudo<
"s_call_b64",
(outs SReg_64:$sdst),
(ins s16imm:$simm16),
"$sdst, $simm16"> {
let isCall = 1;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SOPC Instructions // SOPC Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SOPCe <bits<7> op> : Enc32 { class SOPCe <bits<7> op> : Enc32 {
bits<8> src0; bits<8> src0;
bits<8> src1; bits<8> src1;
▲ Show 20 Lines • Show All 637 Lines • ▼ Show 20 Lines
def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>; def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>;
def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>; def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>;
def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>; def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>; def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>; def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
//def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments //def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>, def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
Select_vi<S_SETREG_IMM32_B32.Mnemonic>; Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>;

test/MC/AMDGPU/data.s

// We check that unrecognized opcodes are disassembled by llvm-objdump as data using the .long directive // We check that unrecognized opcodes are disassembled by llvm-objdump as data using the .long directive
// and any trailing bytes are disassembled using the .byte directive // and any trailing bytes are disassembled using the .byte directive
// RUN: llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=gfx900 -show-encoding %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s // RUN: llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=gfx900 -show-encoding %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s
.text .text
v_mov_b32 v7, s24 v_mov_b32 v7, s24
v_mov_b32 v8, s25 v_mov_b32 v8, s25
.long 0xabadc0de .long 0xabadc0de
s_nop 0 s_nop 0
s_endpgm s_endpgm
.long 0xbadc0de1, 0xbadc0de2, 0xbadc0de3, 0xbadc0de4 .long 0xabadc0d1, 0xabadc0d2, 0xabadc0d3, 0xabadc0d4
.byte 0x0a, 0x0b .byte 0x0a, 0x0b
.byte 0x0c .byte 0x0c
// CHECK: .text // CHECK: .text
// CHECK: v_mov_b32 // CHECK: v_mov_b32
// CHECK: v_mov_b32 // CHECK: v_mov_b32
// CHECK: .long 0xabadc0de // CHECK: .long 0xabadc0de
// CHECK_SAME: : ABADC0DE // CHECK_SAME: : ABADC0DE
// CHECK: s_endpgm // CHECK: s_endpgm
// CHECK: .long 0xbadc0de1 // CHECK: .long 0xabadc0d1
// CHECK: .long 0xbadc0de2 // CHECK: .long 0xabadc0d2
// CHECK: .long 0xbadc0de3 // CHECK: .long 0xabadc0d3
// CHECK: .long 0xbadc0de4 // CHECK: .long 0xabadc0d4
// CHECK: .byte 0x0a, 0x0b, 0x0c // CHECK: .byte 0x0a, 0x0b, 0x0c
// CHECK-SAME: : 0A 0B 0C // CHECK-SAME: : 0A 0B 0C
// CHECK-NOT: .long // CHECK-NOT: .long

test/MC/AMDGPU/sopk.s

// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOSI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOVI %s
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
s_movk_i32 s2, 0x6 s_movk_i32 s2, 0x6
// GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0] // GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
s_cmovk_i32 s2, 0x6 s_cmovk_i32 s2, 0x6
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
s_setreg_imm32_b32 0x6, 0xff s_setreg_imm32_b32 0x6, 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] // SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] // VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
// HW register identifier, non-default offset/width // HW register identifier, non-default offset/width
s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00] // SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00] // VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
s_call_b64 s[12:13], 12609
// GFX9: s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba]
// NOSICIVI: error: instruction not supported on this GPU
s_call_b64 s[100:101], 12609
// GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
// NOSICIVI: error: instruction not supported on this GPU
s_call_b64 s[10:11], 49617
// GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
// NOSICIVI: error: instruction not supported on this GPU

test/MC/Disassembler/AMDGPU/sopk_gfx9.txt

  • This file was added.
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba]
0x41,0x31,0x8a,0xba
# GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
0x41,0x31,0xe4,0xba
# GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
0xd1,0xc1,0x8a,0xba