[AMDGPU][MC][GFX9] Added s_call_b64

[dp]

Summary

See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843

I had to correct a lit test data.s because seemingly unused combination of bits

.long 0xbadc0de1

turned out to be a valid gfx9 instruction:

s_call_b64 s[92:93], 0xde1

Isn't it curious?

[artem.tamazov]

LGTM

llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

def S_SETREG_IMM32_B32 : SOPK_Pseudo <
   (outs), (ins i32imm:$imm, hwreg:$simm16),
   "$simm16, $imm"> {
   let Size = 8; // Unlike every other SOPK instruction.
   let has_sdst = 0;
 }
 
 } // End hasSideEffects = 1
 
+let SubtargetPredicate = isGFX9 in {
+  def S_CALL_B64 : SOPK_Pseudo<
+      "s_call_b64",
+      (outs SReg_64:$sdst),
+      (ins s16imm:$simm16),
+      "$sdst, $simm16"> {
+    let isCall = 1;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // SOPC Instructions
 //===----------------------------------------------------------------------===//
 
 class SOPCe <bits<7> op> : Enc32 {
   bits<8> src0;
   bits<8> src1;
 

 def S_MULK_I32_vi          : SOPK_Real_vi <0x0F, S_MULK_I32>;
 def S_CBRANCH_I_FORK_vi    : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
 def S_GETREG_B32_vi        : SOPK_Real_vi <0x11, S_GETREG_B32>;
 def S_SETREG_B32_vi        : SOPK_Real_vi <0x12, S_SETREG_B32>;
 //def S_GETREG_REGRD_B32_vi  : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
 def S_SETREG_IMM32_B32_vi  : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
                              Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
 
+def S_CALL_B64_vi          : SOPK_Real_vi <0x15, S_CALL_B64>;
+
 //===----------------------------------------------------------------------===//
 // SOP1 - GFX9.
 //===----------------------------------------------------------------------===//
 
 def S_ANDN1_SAVEEXEC_B64_vi   : SOP1_Real_vi<0x33, S_ANDN1_SAVEEXEC_B64>;
 def S_ORN1_SAVEEXEC_B64_vi    : SOP1_Real_vi<0x34, S_ORN1_SAVEEXEC_B64>;
 def S_ANDN1_WREXEC_B64_vi     : SOP1_Real_vi<0x35, S_ANDN1_WREXEC_B64>;
 def S_ANDN2_WREXEC_B64_vi     : SOP1_Real_vi<0x36, S_ANDN2_WREXEC_B64>;
 def S_BITREPLICATE_B64_B32_vi : SOP1_Real_vi<0x37, S_BITREPLICATE_B64_B32>;

llvm/trunk/test/MC/AMDGPU/data.s

 // We check that unrecognized opcodes are disassembled by llvm-objdump as data using the .long directive 
 // and any trailing bytes are disassembled using the .byte directive
 // RUN: llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=gfx900 -show-encoding %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s
 
 .text
         v_mov_b32     v7, s24
-  v_mov_b32     v8, s25
-  .long         0xabadc0de
-  s_nop         0
-  s_endpgm                  
-  .long         0xbadc0de1, 0xbadc0de2, 0xbadc0de3, 0xbadc0de4
-  .byte         0x0a, 0x0b
-  .byte         0x0c
+  v_mov_b32     v8, s25
+  .long         0xabadc0de
+  s_nop         0
+  s_endpgm
+  .long         0xabadc0d1, 0xabadc0d2, 0xabadc0d3, 0xabadc0d4
+  .byte         0x0a, 0x0b
+  .byte         0x0c
 
 // CHECK: .text
 // CHECK: v_mov_b32
 // CHECK: v_mov_b32
 // CHECK: .long 0xabadc0de
 // CHECK_SAME: : ABADC0DE
 // CHECK: s_endpgm
-// CHECK: .long 0xbadc0de1
-// CHECK: .long 0xbadc0de2
-// CHECK: .long 0xbadc0de3
-// CHECK: .long 0xbadc0de4
+// CHECK: .long 0xabadc0d1
+// CHECK: .long 0xabadc0d2
+// CHECK: .long 0xabadc0d3
+// CHECK: .long 0xabadc0d4
 // CHECK: .byte 0x0a, 0x0b, 0x0c
 // CHECK-SAME: : 0A 0B 0C
 // CHECK-NOT: .long

llvm/trunk/test/MC/AMDGPU/sopk.s

 // HW register identifier, non-default offset/width
 s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
 // SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
 // VI9:  s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
 
 s_endpgm_ordered_ps_done
 // GFX9:     s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 // NOSICIVI: error: instruction not supported on this GPU
+
+s_call_b64 s[12:13], 12609
+// GFX9:     s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_call_b64 s[100:101], 12609
+// GFX9:     s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_call_b64 s[10:11], 49617
+// GFX9:     s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+// NOSICIVI: error: instruction not supported on this GPU

llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
 
 # GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 0x00,0x00,0x9e,0xbf
+
+# GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba]
+0x41,0x31,0x8a,0xba
+
+# GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+0x41,0x31,0xe4,0xba
+
+# GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+0xd1,0xc1,0x8a,0xba