[PowerPC] Add a Memory Latency Mutation to the scheduler

[stefanp]

Summary

Loads and Stores that depend on the same address should be scheduled apart because we don't want a load that is waiting for a store to finish or a store that is waiting for a load to finish.

This patch depends on D45265 and so that patch would have to go in first.

[lei]

lib/Target/PowerPC/PPCSubtarget.cpp

53

Maybe do an early exit here:

if (!SU.getInstr()->mayLoad() && ! SU.getInstr()->mayStore())
  continue;

Then we don't need to nest the two for loops below.

[stefanp]

Modifications based on review comments.

[stefanp]

No longer working on this.

lib/Target/PowerPC/PPCSubtarget.h

const PPCRegisterInfo *getRegisterInfo() const override {
     return &getInstrInfo()->getRegisterInfo();
   }
   const PPCTargetMachine &getTargetMachine() const { return TM; }
 
   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
   /// so that we can use initializer lists for subtarget initialization.
   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
+  struct MemLatencyMutation : public ScheduleDAGMutation {
+    void apply(ScheduleDAGInstrs *DAG) override;
+  };
+
 private:
   void initializeEnvironment();
   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 
 public:
   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
   ///
   bool isPPC64() const;

lib/Target/PowerPC/PPCSubtarget.cpp

 
 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;
 }
 
+void PPCSubtarget::MemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
+  for (SUnit &SU : DAG->SUnits) {
+    // Looking for loads and stores.
+    if (!SU.getInstr()->mayLoad() && !SU.getInstr()->mayStore()) 
+      continue;
+
+    // If we have a memory dependency then set the latency to 4 cycles.
+    // The reason 4 is picked is because it is the best case scenario for a
+    // load when we get a cache hit.
+    for (SDep &Dep :  SU.Succs) {
+      if (Dep.isNormalMemory())
+        Dep.setLatency(4);
+    }
+    for (SDep &Dep :  SU.Preds) {
+      if (Dep.isNormalMemory())
+        Dep.setLatency(4);
+    }
+  }
+}
+
 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
               TargetTriple.getArch() == Triple::ppc64le),
       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       InstrInfo(*this), TLInfo(TM, *this) {}
 

lib/Target/PowerPC/PPCTargetMachine.cpp

 public:
   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
     : TargetPassConfig(TM, PM) {}
 
   PPCTargetMachine &getPPCTargetMachine() const {
     return getTM<PPCTargetMachine>();
   }
 
+  ScheduleDAGInstrs *
+  createMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
+    DAG->addMutation(llvm::make_unique<PPCSubtarget::MemLatencyMutation>());
+    return DAG;
+  }
+
+  ScheduleDAGInstrs *
+  createPostMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
+    DAG->addMutation(llvm::make_unique<PPCSubtarget::MemLatencyMutation>());
+    return DAG;
+  }
+
   void addIRPasses() override;
   bool addPreISel() override;
   bool addILPOpts() override;
   bool addInstSelector() override;
   void addMachineSSAOptimization() override;
   void addPreRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;