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Differential D45097

[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
ClosedPublic

Authored by dp on Mar 30 2018, 9:12 AM.

Details

Reviewers
arsenm
artem.tamazov
timcorringham
Commits
rGb181c7312e17: [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
rL328988: [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
Summary

See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Mar 30 2018, 9:12 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptMar 30 2018, 9:12 AM
arsenm accepted this revision.Mar 30 2018, 9:37 AM

LGTM

This revision is now accepted and ready to land.Mar 30 2018, 9:37 AM
Closed by commit rL328988: [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16 (authored by dpreobra). · Explain WhyApr 2 2018, 10:12 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 2 2018, 10:12 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
28 lines
24 lines
15 lines
25 lines
Disassembler/
AMDGPU/
18 lines
21 lines
21 lines

Diff 140645

llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td

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let SubtargetPredicate = isGFX9 in { let SubtargetPredicate = isGFX9 in {
let Constraints = "$vdst = $src1, $vdst1 = $src0", let Constraints = "$vdst = $src1, $vdst1 = $src0",
DisableEncoding="$vdst1,$src1", DisableEncoding="$vdst1,$src1",
SchedRW = [Write64Bit, Write64Bit] in { SchedRW = [Write64Bit, Write64Bit] in {
// Never VOP3. Takes as long as 2 v_mov_b32s // Never VOP3. Takes as long as 2 v_mov_b32s
def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>; def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>;
} }
defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
} // End SubtargetPredicate = isGFX9 } // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target // Target
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SI // SI
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defm V_CEIL_F16 : VOP1_Real_vi <0x45>; defm V_CEIL_F16 : VOP1_Real_vi <0x45>;
defm V_TRUNC_F16 : VOP1_Real_vi <0x46>; defm V_TRUNC_F16 : VOP1_Real_vi <0x46>;
defm V_RNDNE_F16 : VOP1_Real_vi <0x47>; defm V_RNDNE_F16 : VOP1_Real_vi <0x47>;
defm V_FRACT_F16 : VOP1_Real_vi <0x48>; defm V_FRACT_F16 : VOP1_Real_vi <0x48>;
defm V_SIN_F16 : VOP1_Real_vi <0x49>; defm V_SIN_F16 : VOP1_Real_vi <0x49>;
defm V_COS_F16 : VOP1_Real_vi <0x4a>; defm V_COS_F16 : VOP1_Real_vi <0x4a>;
defm V_SWAP_B32 : VOP1Only_Real_vi <0x51>; defm V_SWAP_B32 : VOP1Only_Real_vi <0x51>;
defm V_SAT_PK_U8_I16 : VOP1_Real_vi<0x4f>;
defm V_CVT_NORM_I16_F16 : VOP1_Real_vi<0x4d>;
defm V_CVT_NORM_U16_F16 : VOP1_Real_vi<0x4e>;
// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
// indexing mode. vdst can't be treated as a def for codegen purposes, // indexing mode. vdst can't be treated as a def for codegen purposes,
// and an implicit use and def of the super register should be added. // and an implicit use and def of the super register should be added.
def V_MOV_B32_indirect : VPseudoInstSI<(outs), def V_MOV_B32_indirect : VPseudoInstSI<(outs),
(ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>, (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,
PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst, PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
getVOPSrc0ForVT<i32>.ret:$src0)> { getVOPSrc0ForVT<i32>.ret:$src0)> {
let VOP1 = 1; let VOP1 = 1;
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llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s

// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
v_swap_b32 v1, v2 v_swap_b32 v1, v2
// GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e] // GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
// NOVI: :1: error: instruction not supported on this GPU // NOVI: :1: error: instruction not supported on this GPU
// FIXME: Error for it requiring VOP1 encoding // FIXME: Error for it requiring VOP1 encoding
v_swap_b32_e32 v1, v2 v_swap_b32_e32 v1, v2
// GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e] // GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
// NOVI: :1: error: instruction not supported on this GPU // NOVI: :1: error: instruction not supported on this GPU
v_cvt_norm_i16_f16 v5, v1
// GFX9: v_cvt_norm_i16_f16_e32 v5, v1 ; encoding: [0x01,0x9b,0x0a,0x7e]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_i16_f16 v5, -4.0
// GFX9: v_cvt_norm_i16_f16_e32 v5, -4.0 ; encoding: [0xf7,0x9a,0x0a,0x7e]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_i16_f16 v5, 0xfe0b
// GFX9: v_cvt_norm_i16_f16_e32 v5, 0xfe0b ; encoding: [0xff,0x9a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_u16_f16 v5, s101
// GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
// NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16 v255, v1
// GFX9: v_sat_pk_u8_i16_e32 v255, v1 ; encoding: [0x01,0x9f,0xfe,0x7f]
// NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16 v5, -1
// GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
// NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16 v5, 0x3f717273
// GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
// NOVI: error: instruction not supported on this GPU

llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s

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v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04] // GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04] // GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04] // GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
v_cvt_norm_i16_f16_e64 v5, -v1
// GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_i16_f16_e64 v5, |v1|
// GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_u16_f16_e64 v5, -v1
// GFX9: v_cvt_norm_u16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
// NOVI: error: instruction not supported on this GPU
v_cvt_norm_u16_f16_e64 v5, |v1|
// GFX9: v_cvt_norm_u16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16_e64 v5, -1
// GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
v_sat_pk_u8_i16_e64 v5, v255
// GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
// NOVI: error: instruction not supported on this GPU

llvm/trunk/test/MC/AMDGPU/vop_dpp.s

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// NOSICI: error: // NOSICI: error:
// VI9: v_sin_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x92,0x02,0x7e,0x00,0x01,0x09,0xa1] // VI9: v_sin_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x92,0x02,0x7e,0x00,0x01,0x09,0xa1]
v_sin_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_sin_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
// NOSICI: error: // NOSICI: error:
// VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1] // VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
v_cos_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_cos_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
// GFX9: v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
// GFX9: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
// GFX9: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
// NOSICI: error
// NOVI: error
v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Check VOP2 opcodes // Check VOP2 opcodes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp) // ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp)
// NOSICI: error: // NOSICI: error:
// VI9: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff] // VI9: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff]
v_mac_f32 v0, v0, v0 row_shl:1 v_mac_f32 v0, v0, v0 row_shl:1
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llvm/trunk/test/MC/AMDGPU/vop_sdwa.s

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// NOSICI: error: // NOSICI: error:
// GFX89: v_sin_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x92,0x02,0x7e,0x00,0x06,0x05,0x00] // GFX89: v_sin_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x92,0x02,0x7e,0x00,0x06,0x05,0x00]
v_sin_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 v_sin_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
// NOSICI: error: // NOSICI: error:
// GFX89: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00] // GFX89: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
v_cos_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 v_cos_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
// GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
// GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x05,0x00]
// NOSICI: error
// NOVI: error
v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
// GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
// NOSICI: error
// NOVI: error
v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Check VOP2 opcodes // Check VOP2 opcodes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NOSICI: error: // NOSICI: error:
// GFX89: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x02] // GFX89: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x02]
v_add_f32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
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// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02]
v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02]
v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
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llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt

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0xf9 0x90 0x02 0x7e 0x00 0x06 0x05 0x00 0xf9 0x90 0x02 0x7e 0x00 0x06 0x05 0x00
# GFX9: v_sin_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x92,0x02,0x7e,0x00,0x06,0x05,0x00] # GFX9: v_sin_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x92,0x02,0x7e,0x00,0x06,0x05,0x00]
0xf9 0x92 0x02 0x7e 0x00 0x06 0x05 0x00 0xf9 0x92 0x02 0x7e 0x00 0x06 0x05 0x00
# GFX9: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00] # GFX9: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
0xf9 0x94 0x02 0x7e 0x00 0x06 0x05 0x00 0xf9 0x94 0x02 0x7e 0x00 0x06 0x05 0x00
# GFX9: v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00]
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00
# GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00
# GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00
# GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00
# GFX9: v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00]
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00
# GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00
#-----------------------------------------------------------------------------# #-----------------------------------------------------------------------------#
# VOP2 # VOP2
#-----------------------------------------------------------------------------# #-----------------------------------------------------------------------------#
# GFX9: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x06] # GFX9: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x06]
0xf9 0x00 0x00 0x02 0x00 0x06 0x05 0x06 0xf9 0x00 0x00 0x02 0x00 0x06 0x05 0x06
# GFX9: v_min_f32_sdwa v0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x36,0x06,0x02] # GFX9: v_min_f32_sdwa v0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x36,0x06,0x02]
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llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e] # GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
0x02 0xa3 0x02 0x7e 0x02 0xa3 0x02 0x7e
# GFX9: v_cvt_norm_i16_f16_e32 v255, v1 ; encoding: [0x01,0x9b,0xfe,0x7f]
0x01,0x9b,0xfe,0x7f
# GFX9: v_cvt_norm_i16_f16_e32 v5, 0.5 ; encoding: [0xf0,0x9a,0x0a,0x7e]
0xf0,0x9a,0x0a,0x7e
# GFX9: v_cvt_norm_i16_f16_e32 v5, 0x3456 ; encoding: [0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00]
0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00
# GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
0x65,0x9c,0x0a,0x7e
# GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e]
0xff,0x9f,0x0a,0x7e
# GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
0xc1,0x9e,0x0a,0x7e
# GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

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# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04] # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04 0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04] # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04 0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
# GFX9: v_add_f64 v[5:6], xnack_mask, v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00] # GFX9: v_add_f64 v[5:6], xnack_mask, v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00]
0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00 0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00
# GFX9: v_cvt_norm_i16_f16_e64 v5, -4.0 ; encoding: [0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00]
0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00
# GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20
# GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00
# GFX9: v_cvt_norm_u16_f16_e64 v255, v1 ; encoding: [0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00
# GFX9: v_cvt_norm_u16_f16_e64 v5, v255 ; encoding: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]
0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00
# GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00
# GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00