Skip to content

Commit b181c73

Browse files
dpreobradpreobra
committedApr 2, 2018
[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847 Differential Revision: https://reviews.llvm.org/D45097 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328988
·
llvmorg-21-initllvmorg-7.0.0-rc1
1 parent 95ab758 commit b181c73

File tree

8 files changed

+160
-0
lines changed

8 files changed

+160
-0
lines changed
 

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

+8
Original file line numberDiff line numberDiff line change
@@ -382,6 +382,10 @@ let SubtargetPredicate = isGFX9 in {
382382
def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>;
383383
}
384384

385+
defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
386+
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
387+
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
388+
385389
} // End SubtargetPredicate = isGFX9
386390

387391
//===----------------------------------------------------------------------===//
@@ -612,6 +616,10 @@ defm V_SIN_F16 : VOP1_Real_vi <0x49>;
612616
defm V_COS_F16 : VOP1_Real_vi <0x4a>;
613617
defm V_SWAP_B32 : VOP1Only_Real_vi <0x51>;
614618

619+
defm V_SAT_PK_U8_I16 : VOP1_Real_vi<0x4f>;
620+
defm V_CVT_NORM_I16_F16 : VOP1_Real_vi<0x4d>;
621+
defm V_CVT_NORM_U16_F16 : VOP1_Real_vi<0x4e>;
622+
615623
// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
616624
// indexing mode. vdst can't be treated as a def for codegen purposes,
617625
// and an implicit use and def of the super register should be added.

‎llvm/test/MC/AMDGPU/vop1-gfx9.s

+28
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,31 @@ v_swap_b32 v1, v2
1111
v_swap_b32_e32 v1, v2
1212
// GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
1313
// NOVI: :1: error: instruction not supported on this GPU
14+
15+
v_cvt_norm_i16_f16 v5, v1
16+
// GFX9: v_cvt_norm_i16_f16_e32 v5, v1 ; encoding: [0x01,0x9b,0x0a,0x7e]
17+
// NOVI: error: instruction not supported on this GPU
18+
19+
v_cvt_norm_i16_f16 v5, -4.0
20+
// GFX9: v_cvt_norm_i16_f16_e32 v5, -4.0 ; encoding: [0xf7,0x9a,0x0a,0x7e]
21+
// NOVI: error: instruction not supported on this GPU
22+
23+
v_cvt_norm_i16_f16 v5, 0xfe0b
24+
// GFX9: v_cvt_norm_i16_f16_e32 v5, 0xfe0b ; encoding: [0xff,0x9a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
25+
// NOVI: error: instruction not supported on this GPU
26+
27+
v_cvt_norm_u16_f16 v5, s101
28+
// GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
29+
// NOVI: error: instruction not supported on this GPU
30+
31+
v_sat_pk_u8_i16 v255, v1
32+
// GFX9: v_sat_pk_u8_i16_e32 v255, v1 ; encoding: [0x01,0x9f,0xfe,0x7f]
33+
// NOVI: error: instruction not supported on this GPU
34+
35+
v_sat_pk_u8_i16 v5, -1
36+
// GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
37+
// NOVI: error: instruction not supported on this GPU
38+
39+
v_sat_pk_u8_i16 v5, 0x3f717273
40+
// GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
41+
// NOVI: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/vop3-gfx9.s

+24
Original file line numberDiff line numberDiff line change
@@ -421,3 +421,27 @@ v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
421421

422422
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
423423
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
424+
425+
v_cvt_norm_i16_f16_e64 v5, -v1
426+
// GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
427+
// NOVI: error: instruction not supported on this GPU
428+
429+
v_cvt_norm_i16_f16_e64 v5, |v1|
430+
// GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
431+
// NOVI: error: instruction not supported on this GPU
432+
433+
v_cvt_norm_u16_f16_e64 v5, -v1
434+
// GFX9: v_cvt_norm_u16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
435+
// NOVI: error: instruction not supported on this GPU
436+
437+
v_cvt_norm_u16_f16_e64 v5, |v1|
438+
// GFX9: v_cvt_norm_u16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
439+
// NOVI: error: instruction not supported on this GPU
440+
441+
v_sat_pk_u8_i16_e64 v5, -1
442+
// GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
443+
// NOVI: error: instruction not supported on this GPU
444+
445+
v_sat_pk_u8_i16_e64 v5, v255
446+
// GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
447+
// NOVI: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/vop_dpp.s

+15
Original file line numberDiff line numberDiff line change
@@ -335,6 +335,21 @@ v_sin_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
335335
// VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
336336
v_cos_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
337337

338+
// GFX9: v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
339+
// NOSICI: error
340+
// NOVI: error
341+
v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
342+
343+
// GFX9: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
344+
// NOSICI: error
345+
// NOVI: error
346+
v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
347+
348+
// GFX9: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
349+
// NOSICI: error
350+
// NOVI: error
351+
v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
352+
338353
//===----------------------------------------------------------------------===//
339354
// Check VOP2 opcodes
340355
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AMDGPU/vop_sdwa.s

+25
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,31 @@ v_sin_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
340340
// GFX89: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
341341
v_cos_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
342342

343+
// GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
344+
// NOSICI: error
345+
// NOVI: error
346+
v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
347+
348+
// GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
349+
// NOSICI: error
350+
// NOVI: error
351+
v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
352+
353+
// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
354+
// NOSICI: error
355+
// NOVI: error
356+
v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
357+
358+
// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x05,0x00]
359+
// NOSICI: error
360+
// NOVI: error
361+
v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
362+
363+
// GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
364+
// NOSICI: error
365+
// NOVI: error
366+
v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
367+
343368
//===----------------------------------------------------------------------===//
344369
// Check VOP2 opcodes
345370
//===----------------------------------------------------------------------===//

‎llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt

+18
Original file line numberDiff line numberDiff line change
@@ -224,6 +224,24 @@
224224
# GFX9: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
225225
0xf9 0x94 0x02 0x7e 0x00 0x06 0x05 0x00
226226

227+
# GFX9: v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00]
228+
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00
229+
230+
# GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
231+
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00
232+
233+
# GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
234+
0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00
235+
236+
# GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
237+
0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00
238+
239+
# GFX9: v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00]
240+
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00
241+
242+
# GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
243+
0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00
244+
227245
#-----------------------------------------------------------------------------#
228246
# VOP2
229247
#-----------------------------------------------------------------------------#

‎llvm/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt

+21
Original file line numberDiff line numberDiff line change
@@ -2,3 +2,24 @@
22

33
# GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
44
0x02 0xa3 0x02 0x7e
5+
6+
# GFX9: v_cvt_norm_i16_f16_e32 v255, v1 ; encoding: [0x01,0x9b,0xfe,0x7f]
7+
0x01,0x9b,0xfe,0x7f
8+
9+
# GFX9: v_cvt_norm_i16_f16_e32 v5, 0.5 ; encoding: [0xf0,0x9a,0x0a,0x7e]
10+
0xf0,0x9a,0x0a,0x7e
11+
12+
# GFX9: v_cvt_norm_i16_f16_e32 v5, 0x3456 ; encoding: [0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00]
13+
0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00
14+
15+
# GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
16+
0x65,0x9c,0x0a,0x7e
17+
18+
# GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e]
19+
0xff,0x9f,0x0a,0x7e
20+
21+
# GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
22+
0xc1,0x9e,0x0a,0x7e
23+
24+
# GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
25+
0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f

‎llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

+21
Original file line numberDiff line numberDiff line change
@@ -671,3 +671,24 @@
671671

672672
# GFX9: v_add_f64 v[5:6], xnack_mask, v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00]
673673
0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00
674+
675+
# GFX9: v_cvt_norm_i16_f16_e64 v5, -4.0 ; encoding: [0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00]
676+
0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00
677+
678+
# GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
679+
0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20
680+
681+
# GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
682+
0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00
683+
684+
# GFX9: v_cvt_norm_u16_f16_e64 v255, v1 ; encoding: [0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
685+
0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00
686+
687+
# GFX9: v_cvt_norm_u16_f16_e64 v5, v255 ; encoding: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]
688+
0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00
689+
690+
# GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
691+
0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00
692+
693+
# GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
694+
0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00

0 commit comments

Comments
 (0)
Please sign in to comment.