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Differential D44825

[AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x
ClosedPublic

Authored by dp on Mar 23 2018, 5:16 AM.

Details

Reviewers
arsenm
artem.tamazov
timcorringham
Commits
rGa917e8858520: [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x
rL328707: [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x
Summary

See bug 36835: https://bugs.llvm.org/show_bug.cgi?id=36835

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Mar 23 2018, 5:16 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptMar 23 2018, 5:16 AM
artem.tamazov accepted this revision.Mar 23 2018, 7:51 AM

LGTM

This revision is now accepted and ready to land.Mar 23 2018, 7:51 AM
Closed by commit rL328707: [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x (authored by dpreobra). · Explain WhyMar 28 2018, 7:56 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptMar 28 2018, 7:56 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
10 lines
test/
MC/
AMDGPU/
48 lines
Disassembler/
AMDGPU/
22 lines

Diff 140075

llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td

Show First 20 Lines • Show All 943 Lines • ▼ Show 20 Lines
defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Pseudo_Stores < defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Pseudo_Stores <
"buffer_store_byte_d16_hi", VGPR_32, i32 "buffer_store_byte_d16_hi", VGPR_32, i32
>; >;
defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores < defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores <
"buffer_store_short_d16_hi", VGPR_32, i32 "buffer_store_short_d16_hi", VGPR_32, i32
>; >;
defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Pseudo_Loads <
"buffer_load_format_d16_hi_x", VGPR_32
>;
defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores <
"buffer_store_format_d16_hi_x", VGPR_32
>;
} // End HasD16LoadStore } // End HasD16LoadStore
def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1", def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
int_amdgcn_buffer_wbinvl1>; int_amdgcn_buffer_wbinvl1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MTBUF Instructions // MTBUF Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 981 Lines • ▼ Show 20 Lines
defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Real_AllAddr_vi <0x20>; defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Real_AllAddr_vi <0x20>;
defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x21>; defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x21>;
defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Real_AllAddr_vi <0x22>; defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Real_AllAddr_vi <0x22>;
defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x23>; defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x23>;
defm BUFFER_LOAD_SHORT_D16 : MUBUF_Real_AllAddr_vi <0x24>; defm BUFFER_LOAD_SHORT_D16 : MUBUF_Real_AllAddr_vi <0x24>;
defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Real_AllAddr_vi <0x25>; defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Real_AllAddr_vi <0x25>;
defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x26>;
defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x27>;
defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_vi <0x40>; defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_vi <0x40>;
defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_vi <0x41>; defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_vi <0x41>;
defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_vi <0x42>; defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_vi <0x42>;
defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_vi <0x43>; defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_vi <0x43>;
defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_vi <0x44>; defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_vi <0x44>;
defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_vi <0x45>; defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_vi <0x45>;
defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_vi <0x46>; defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_vi <0x46>;
defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_vi <0x47>; defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_vi <0x47>;
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llvm/trunk/test/MC/AMDGPU/mubuf-gfx9.s

Show All 26 Lines
buffer_store_byte_d16_hi v1, off, s[4:7], s1 buffer_store_byte_d16_hi v1, off, s[4:7], s1
// GFX9: buffer_store_byte_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x01,0x01,0x01] // GFX9: buffer_store_byte_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x01,0x01,0x01]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
buffer_store_short_d16_hi v1, off, s[4:7], s1 buffer_store_short_d16_hi v1, off, s[4:7], s1
// GFX9: buffer_store_short_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x01,0x01] // GFX9: buffer_store_short_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x01,0x01]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
buffer_load_format_d16_hi_x v5, off, s[8:11], s3
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error: instruction not supported on this GPU
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x9a,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_store_format_d16_hi_x v255, off, s[12:15], s4
// GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 ; encoding: [0x00,0x00,0x9c,0xe0,0x00,0xff,0x03,0x04]
// VI-ERR: error: instruction not supported on this GPU
buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
// GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe0,0x00,0xff,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095
// GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095
// GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc
// GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc
// GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error

llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_gfx9.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc slc ; encoding: [0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03]
0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04