[AMDGPU][MC] Added ds_add_src2_f32

[dp]

Summary

See bug 36833: https://bugs.llvm.org/show_bug.cgi?id=36833

[arsenm]

I see this listed in the gfx9 manual, but not VI. Does this need the subtarget feature?

[dp]

In D44779#1045695, @arsenm wrote:

I see this listed in the gfx9 manual, but not VI. Does this need the subtarget feature?

I'm not sure. It is not listed in Gfx9_Shader_Programming either.
But it is present in SP3 tables for VI.

Do you know who can help with this question?
Maybe Tony?

[dp]

So Dan Clifton confirmed it is gfx7.
But maybe it would be safer to support this opcode for gfx8/9 only to mimic SP3 assembler?
I'm not sure about gfx7.

[artem.tamazov]

In D44779#1046500, @dp wrote:

But maybe it would be safer to support this opcode for gfx8/9 only to mimic SP3 assembler?

I think that supporting this inst for gfx7 would not break the sp3 compatibility. And we do not need to support all the quirks of SP3)) So it's up to you. I would prefer the solution which would be the simplest and the robustness one.

[artem.tamazov]

LGTM

llvm/trunk/lib/Target/AMDGPU/DSInstructions.td

 
 let Uses = [EXEC] in {
 def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
                                        int_amdgcn_ds_permute>;
 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
                                        int_amdgcn_ds_bpermute>;
 }
 
+def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
+
 } // let SubtargetPredicate = isVI
 
 //===----------------------------------------------------------------------===//
 // DS Patterns
 //===----------------------------------------------------------------------===//
 
 def : GCNPat <
   (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),

 def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
 def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
 def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
 def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
 def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
 def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
 def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
 def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
+def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
 def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
 def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
 def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
 def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
 def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
 def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
 def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
 def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;

llvm/trunk/test/MC/AMDGPU/ds.s

 //===----------------------------------------------------------------------===//
 // Checks for 16-bit Offsets
 //===----------------------------------------------------------------------===//
 
 ds_add_u32 v2, v4 offset:16
 // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 // VI:   ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 
+ds_add_src2_f32 v255 offset:65535
+// NOSICI: error
+// VI: ds_add_src2_f32 v255 offset:65535 ; encoding: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v0 offset:4 gds
+// NOSICI: error
+// VI: ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+
 //===----------------------------------------------------------------------===//
 // Checks for 2 8-bit Offsets
 //===----------------------------------------------------------------------===//
 
 ds_write_src2_b32 v2 offset:2052
 // SICI: ds_write_src2_b32 v2 offset:2052 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
 // VI:   ds_write_src2_b32 v2 offset:2052 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
 

llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

 # VI:   ds_read_b64 v[8:9], v2 ; encoding: [0x00,0x00,0xec,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0xec 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read2_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xee,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0xee 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0xf0 0xd8 0x02 0x00 0x00 0x08
+
+# VI:   ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00