[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU

[t-tye]

Summary

• Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
• Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.

[kzhuravl]

Should the same be done for "hcc" (it is currently in the docs)?

[yaxunl]

LTGM. Thanks!

[arsenm]

include/llvm/ADT/Triple.h

205 ↗

(On Diff #135806)

This isn't related to this. This was used in the x86 OpenCL implementation to change some lib calls I believe

lib/Target/AMDGPU/AMDGPUSubtarget.h

214–217 ↗

(On Diff #135806)

The naming of this is wrong. We don't want to specify the language, I thought the point of this was to specify the size of the kernel segment, so this would have a value and not be a bool indicating a source language

[t-tye]

• Changed to use function attribute that specifies the number of bytes of implicit arguments for OpenCL kernels when using the AMDHSA OS.

[t-tye]

include/llvm/ADT/Triple.h

205 ↗

(On Diff #135806)

Split into separate patch D43895.

[arsenm]

lib/Target/AMDGPU/AMDGPUSubtarget.h

541 ↗

(On Diff #136233)

You don't need this separate check for the attribute existing. getIntegerAttribute essentially does this for you

[t-tye]

Address review comment.

[arsenm]

lib/Target/AMDGPU/AMDGPUSubtarget.h

540–541 ↗

(On Diff #137122)

Is there a maximum value we could default this to instead of 0? I'm a bit worried that if this attribute is missing or mis-specified the program will be broken, i.e. this attribute could only reduce the amount used

[t-tye]

lib/Target/AMDGPU/AMDGPUSubtarget.h

540–541 ↗

(On Diff #137122)

I spoke to @scchan and HCC does not use any implicit arguments, so defaulting to 0 seems the right thing.

[t-tye]

Address review feedback.

Add OpenCL implicit argument description.

Remove unused hcc target triple environment.

[arsenm]

lib/Target/AMDGPU/AMDGPUSubtarget.h

540–541 ↗

(On Diff #137122)

I don't see how what hcc wants is related? What is the maximum value this could be? In general attributes should make things less conservative, not more

[t-tye]

lib/Target/AMDGPU/AMDGPUSubtarget.h

540–541 ↗

(On Diff #137122)

If a language runtime does not need any implicit arguments why would we want to add some space for arguments that are never used? The original code never added implicit arguments unless it was being explicitly requested. Conceptually the maximum number is maxint since a different runtime/OS ABI may want a different set of implicit arguments.

[arsenm]

LGTM

llvm/trunk/docs/AMDGPUUsage.rst

.. table:: AMDGPU Operating Systems
      ============== ============================================================
 
   .. table:: AMDGPU Environments
      :name: amdgpu-environment-table
 
      ============ ==============================================================
      Environment  Description
      ============ ==============================================================
-     *<empty>*    Defaults to ``opencl``.
-     ``opencl``   OpenCL compute kernel (see :ref:`amdgpu-opencl`).
-     ``hcc``      AMD HC language compute kernel (see :ref:`amdgpu-hcc`).
+     *<empty>*    Default.
      ============ ==============================================================
 
 .. _amdgpu-processors:
 
 Processors
 ----------
 
 Use the ``clang -mcpu <Processor>`` option to specify the AMD GPU processor. The

 Source Languages
 ================
 
 .. _amdgpu-opencl:
 
 OpenCL
 ------
 
-When generating code for the OpenCL language the target triple environment
-should be ``opencl`` or ``amdgizcl`` (see :ref:`amdgpu-target-triples`).
-
 When the language is OpenCL the following differences occur:
 
 1. The OpenCL memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
-2. The AMDGPU backend adds additional arguments to the kernel.
+2. The AMDGPU backend appends additional arguments to the kernel's explicit
+   arguments for the AMDHSA OS (see
+   :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
 3. Additional metadata is generated
-   (:ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
+   (see :ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
 
-.. TODO
-   Specify what affect this has. Hidden arguments added. Additional metadata
-   generated.
+  .. table:: OpenCL kernel implicit arguments appended for AMDHSA OS
+     :name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table
+
+     ======== ==== ========= ===========================================
+     Position Byte Byte      Description
+              Size Alignment
+     ======== ==== ========= ===========================================
+     0        8    8         OpenCL Global Offset X
+     1        8    8         OpenCL Global Offset Y
+     2        8    8         OpenCL Global Offset Z
+     3        8    8         OpenCL printf buffer
+     ======== ==== ========= ===========================================
 
 .. _amdgpu-hcc:
 
 HCC
 ---
 
-When generating code for the OpenCL language the target triple environment
-should be ``hcc`` (see :ref:`amdgpu-target-triples`).
-
-When the language is OpenCL the following differences occur:
+When the language is HCC the following differences occur:
 
 1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
 
-.. TODO
-   Specify what affect this has.
-
 Assembler
 ---------
 
 AMDGPU backend has LLVM-MC based assembler which is currently in development.
 It supports AMDGCN GFX6-GFX9.
 
 This section describes general syntax for instructions and operands.
 

llvm/trunk/include/llvm/ADT/Triple.h

enum EnvironmentType {
     Musl,
     MuslEABI,
     MuslEABIHF,
 
     MSVC,
     Itanium,
     Cygnus,
     CoreCLR,
-    OpenCL,
     Simulator,  // Simulator variants of other systems, e.g., Apple's iOS
     LastEnvironmentType = Simulator
   };
   enum ObjectFormatType {
     UnknownObjectFormat,
 
     COFF,
     ELF,

llvm/trunk/lib/Support/Triple.cpp

StringRef Triple::getEnvironmentTypeName(EnvironmentType Kind) {
   case Android: return "android";
   case Musl: return "musl";
   case MuslEABI: return "musleabi";
   case MuslEABIHF: return "musleabihf";
   case MSVC: return "msvc";
   case Itanium: return "itanium";
   case Cygnus: return "cygnus";
   case CoreCLR: return "coreclr";
-  case OpenCL: return "opencl";
   case Simulator: return "simulator";
   }
 
   llvm_unreachable("Invalid EnvironmentType!");
 }
 
 static Triple::ArchType parseBPFArch(StringRef ArchName) {
   if (ArchName.equals("bpf")) {
return StringSwitch<Triple::EnvironmentType>(EnvironmentName)
     .StartsWith("android", Triple::Android)
     .StartsWith("musleabihf", Triple::MuslEABIHF)
     .StartsWith("musleabi", Triple::MuslEABI)
     .StartsWith("musl", Triple::Musl)
     .StartsWith("msvc", Triple::MSVC)
     .StartsWith("itanium", Triple::Itanium)
     .StartsWith("cygnus", Triple::Cygnus)
     .StartsWith("coreclr", Triple::CoreCLR)
-    .StartsWith("opencl", Triple::OpenCL)
     .StartsWith("simulator", Triple::Simulator)
     .Default(Triple::UnknownEnvironment);
 }
 
 static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
   return StringSwitch<Triple::ObjectFormatType>(EnvironmentName)
     .EndsWith("coff", Triple::COFF)
     .EndsWith("elf", Triple::ELF)

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   bool isAmdHsaOS() const {
     return TargetTriple.getOS() == Triple::AMDHSA;
   }
 
   bool isMesa3DOS() const {
     return TargetTriple.getOS() == Triple::Mesa3D;
   }
 
-  bool isOpenCLEnv() const {
-    return TargetTriple.getEnvironment() == Triple::OpenCL ||
-           TargetTriple.getEnvironmentName() == "amdgizcl";
-  }
-
   bool isAmdPalOS() const {
     return TargetTriple.getOS() == Triple::AMDPAL;
   }
 
   Generation getGeneration() const {
     return Gen;
   }
 
public:
   unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
     return isAmdCodeObjectV2(MF) ? 0 : 36;
   }
 
   unsigned getAlignmentForImplicitArgPtr() const {
     return isAmdHsaOS() ? 8 : 4;
   }
 
+  /// \returns Number of bytes of arguments that are passed to a shader or
+  /// kernel in addition to the explicit ones declared for the function.
   unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
     if (isMesaKernel(MF))
       return 16;
-    if (isAmdHsaOS() && isOpenCLEnv())
-      return 32;
-    return 0;
+    return AMDGPU::getIntegerAttribute(
+      MF.getFunction(), "amdgpu-implicitarg-num-bytes", 0);
   }
 
   // Scratch is allocated in 256 dword per wave blocks for the entire
   // wavefront. When viewed from the perspecive of an arbitrary workitem, this
   // is 4-byte aligned.
   unsigned getStackAlignment() const {
     return 4;
   }

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
 
 ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
 
-; HSA-NOENV: kernarg_segment_byte_size = 0
-; HSA-OPENCL: kernarg_segment_byte_size = 32
+; HSA: kernarg_segment_byte_size = 0
 ; MESA: kernarg_segment_byte_size = 16
 
 ; HSA: s_load_dword s0, s[4:5], 0x0
 define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load = load volatile i32, i32 addrspace(4)* %cast
   ret void
 }
 
+; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+
+; HSA: kernarg_segment_byte_size = 32
+; MESA: kernarg_segment_byte_size = 16
+
+; HSA: s_load_dword s0, s[4:5], 0x0
+define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
+  %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+  %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %load = load volatile i32, i32 addrspace(4)* %cast
+  ret void
+}
+
 ; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
 
-; HSA-NOENV: kernarg_segment_byte_size = 112
-; HSA-OPENCL: kernarg_segment_byte_size = 144
+; HSA: kernarg_segment_byte_size = 112
 ; MESA: kernarg_segment_byte_size = 464
 
 ; HSA: s_load_dword s0, s[4:5], 0x1c
 define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load = load volatile i32, i32 addrspace(4)* %cast
   ret void
 }
 
+; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+
+; HSA: kernarg_segment_byte_size = 144
+; MESA: kernarg_segment_byte_size = 464
+
+; HSA: s_load_dword s0, s[4:5], 0x1c
+define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
+  %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+  %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %load = load volatile i32, i32 addrspace(4)* %cast
+  ret void
+}
+
 ; GCN-LABEL: {{^}}func_implicitarg_ptr:
 ; GCN: s_waitcnt
 ; MESA: s_mov_b64 s[8:9], s[6:7]
 ; MESA: s_mov_b32 s11, 0xf000
 ; MESA: s_mov_b32 s10, -1
 ; MESA: buffer_load_dword v0, off, s[8:11], 0
 ; HSA: v_mov_b32_e32 v0, s6
 ; HSA: v_mov_b32_e32 v1, s7
 ; HSA: flat_load_dword v0, v[0:1]
 ; GCN-NEXT: s_waitcnt
 ; GCN-NEXT: s_setpc_b64
-define void @func_implicitarg_ptr() #1 {
+define void @func_implicitarg_ptr() #0 {
+  %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+  %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %load = load volatile i32, i32 addrspace(4)* %cast
+  ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
+; GCN: s_waitcnt
+; MESA: s_mov_b64 s[8:9], s[6:7]
+; MESA: s_mov_b32 s11, 0xf000
+; MESA: s_mov_b32 s10, -1
+; MESA: buffer_load_dword v0, off, s[8:11], 0
+; HSA: v_mov_b32_e32 v0, s6
+; HSA: v_mov_b32_e32 v1, s7
+; HSA: flat_load_dword v0, v[0:1]
+; GCN-NEXT: s_waitcnt
+; GCN-NEXT: s_setpc_b64
+define void @opencl_func_implicitarg_ptr() #0 {
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load = load volatile i32, i32 addrspace(4)* %cast
   ret void
 }
 
 ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-NOENV: kernarg_segment_byte_size = 0
-; HSA-OPENCL: kernarg_segment_byte_size = 32
+; HSA: kernarg_segment_byte_size = 0
 ; MESA: kernarg_segment_byte_size = 16
 ; GCN: s_mov_b64 s[6:7], s[4:5]
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
   call void @func_implicitarg_ptr()
   ret void
 }
 
+; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: kernarg_segment_byte_size = 32
+; MESA: kernarg_segment_byte_size = 16
+; GCN: s_mov_b64 s[6:7], s[4:5]
+; GCN: s_swappc_b64
+define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
+  call void @func_implicitarg_ptr()
+  ret void
+}
+
 ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-OPENCL: kernarg_segment_byte_size = 144
-; HSA-NOENV: kernarg_segment_byte_size = 112
+; HSA: kernarg_segment_byte_size = 112
 ; MESA: kernarg_segment_byte_size = 464
 
 ; HSA: s_add_u32 s6, s4, 0x70
 ; MESA: s_add_u32 s6, s4, 0x1c0
 
 ; GCN: s_addc_u32 s7, s5, 0{{$}}
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
   call void @func_implicitarg_ptr()
   ret void
 }
 
+; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: kernarg_segment_byte_size = 144
+; MESA: kernarg_segment_byte_size = 464
+
+; HSA: s_add_u32 s6, s4, 0x70
+; MESA: s_add_u32 s6, s4, 0x1c0
+
+; GCN: s_addc_u32 s7, s5, 0{{$}}
+; GCN: s_swappc_b64
+define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
+  call void @func_implicitarg_ptr()
+  ret void
+}
+
 ; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
 ; GCN-NOT: s6
 ; GCN-NOT: s7
 ; GCN-NOT: s[6:7]
-define void @func_call_implicitarg_ptr_func() #1 {
+define void @func_call_implicitarg_ptr_func() #0 {
+  call void @func_implicitarg_ptr()
+  ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
+; GCN-NOT: s6
+; GCN-NOT: s7
+; GCN-NOT: s[6:7]
+define void @opencl_func_call_implicitarg_ptr_func() #0 {
   call void @func_implicitarg_ptr()
   ret void
 }
 
 ; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
 ; GCN: s_waitcnt
 ; MESA: s_mov_b64 s[12:13], s[6:7]
 ; MESA: s_mov_b32 s15, 0xf000
 ; MESA: s_mov_b32 s14, -1
 ; MESA: buffer_load_dword v0, off, s[12:15], 0
 ; HSA: v_mov_b32_e32 v0, s6
 ; HSA: v_mov_b32_e32 v1, s7
 ; HSA: flat_load_dword v0, v[0:1]
 ; MESA: s_mov_b32 s10, s14
 ; MESA: s_mov_b32 s11, s15
 ; MESA: buffer_load_dword v0, off, s[8:11], 0
 ; HSA: v_mov_b32_e32 v0, s8
 ; HSA: v_mov_b32_e32 v1, s9
 ; HSA: flat_load_dword v0, v[0:1]
 
 ; GCN: s_waitcnt vmcnt(0)
-define void @func_kernarg_implicitarg_ptr() #1 {
+define void @func_kernarg_implicitarg_ptr() #0 {
+  %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
+  %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+  %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
+  %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
+  %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
+  ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
+; GCN: s_waitcnt
+; MESA: s_mov_b64 s[12:13], s[6:7]
+; MESA: s_mov_b32 s15, 0xf000
+; MESA: s_mov_b32 s14, -1
+; MESA: buffer_load_dword v0, off, s[12:15], 0
+; HSA: v_mov_b32_e32 v0, s6
+; HSA: v_mov_b32_e32 v1, s7
+; HSA: flat_load_dword v0, v[0:1]
+; MESA: s_mov_b32 s10, s14
+; MESA: s_mov_b32 s11, s15
+; MESA: buffer_load_dword v0, off, s[8:11], 0
+; HSA: v_mov_b32_e32 v0, s8
+; HSA: v_mov_b32_e32 v1, s9
+; HSA: flat_load_dword v0, v[0:1]
+
+; GCN: s_waitcnt vmcnt(0)
+define void @opencl_func_kernarg_implicitarg_ptr() #0 {
   %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
   %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
   %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
   ret void
 }
 
 ; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
 ; GCN: s_mov_b64 s[6:7], s[4:5]
 ; HSA: s_add_u32 s8, s6, 0x70
 ; MESA: s_add_u32 s8, s6, 0x1c0
 ; GCN: s_addc_u32 s9, s7, 0
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
   call void @func_kernarg_implicitarg_ptr()
   ret void
 }
 
 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
 
 attributes #0 = { nounwind noinline }
-attributes #1 = { nounwind noinline }
+attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="32" }
 attributes #2 = { nounwind readnone speculatable }

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
 ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
-; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
 
 ; ALL-LABEL: {{^}}test:
 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
 ; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
 
 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
 define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
   %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
   %header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
   %value = load i32, i32 addrspace(4)* %gep
   store i32 %value, i32 addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}test_implicit_alignment
-; HSA-NOENV: kernarg_segment_byte_size = 10
-; HSA-OPENCL: kernarg_segment_byte_size = 48
+; HSA: kernarg_segment_byte_size = 10
 ; OS-MESA3D: kernarg_segment_byte_size = 28
 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
 ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
 ; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
 ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
 ; MESA: buffer_store_dword [[V_VAL]]
 ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
 define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
   %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %val = load i32, i32 addrspace(4)* %arg.ptr
   store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
+; ALL-LABEL: {{^}}opencl_test_implicit_alignment
+; HSA: kernarg_segment_byte_size = 48
+; OS-MESA3D: kernarg_segment_byte_size = 28
+; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
+; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
+; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
+; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
+; MESA: buffer_store_dword [[V_VAL]]
+; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
+define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 {
+  %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+  %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %val = load i32, i32 addrspace(4)* %arg.ptr
+  store i32 %val, i32 addrspace(1)* %out
+  ret void
+}
+
 ; ALL-LABEL: {{^}}test_no_kernargs:
 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
 ; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
 define amdgpu_kernel void @test_no_kernargs() #1 {
   %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
   %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
   %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
   %value = load i32, i32 addrspace(4)* %gep
   store volatile i32 %value, i32 addrspace(1)* undef
   ret void
 }
 
 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
+attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="32" }

llvm/trunk/unittests/ADT/TripleTest.cpp

TEST(TripleTest, ParsedIDs) {
   EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
 
   T = Triple("amdgcn-amd-amdhsa");
   EXPECT_EQ(Triple::amdgcn, T.getArch());
   EXPECT_EQ(Triple::AMD, T.getVendor());
   EXPECT_EQ(Triple::AMDHSA, T.getOS());
   EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
 
-  T = Triple("amdgcn-amd-amdhsa-opencl");
-  EXPECT_EQ(Triple::amdgcn, T.getArch());
-  EXPECT_EQ(Triple::AMD, T.getVendor());
-  EXPECT_EQ(Triple::AMDHSA, T.getOS());
-  EXPECT_EQ(Triple::OpenCL, T.getEnvironment());
-
   T = Triple("amdgcn-amd-amdpal");
   EXPECT_EQ(Triple::amdgcn, T.getArch());
   EXPECT_EQ(Triple::AMD, T.getVendor());
   EXPECT_EQ(Triple::AMDPAL, T.getOS());
   EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
 
   T = Triple("riscv32-unknown-unknown");
   EXPECT_EQ(Triple::riscv32, T.getArch());