[WebAssembly] Add except_ref as a first-class type

[aheejin]

Summary

Add except_ref as a first-class type, according to the Level 1 exception handling proposal.

[aheejin]

rebase

[aheejin]

• Opcode for except_ref has changed to -0x18

[dschuff]

include/llvm/CodeGen/MachineValueType.h

751 ↗

(On Diff #136487)

This seems fishy. What would a caller actually do with a 0-size type? Do we expect this to ever be called? Should it be an unreachable instead?

[aheejin]

rebase + change -0x18 to 0x68 to use uint8_t

[aheejin]

• deleted , at the end to match the previous code

[aheejin]

include/llvm/CodeGen/MachineValueType.h

751 ↗

(On Diff #136487)

Yes, it is called here, while tablegen generates tables. We need this line, because if it's an unreachable, it will crash the LLVM build while running tablegen.

Also we have one more 0 in this CL in this line in lib/Target/WebAssembly/WebAssemblyRegisterInfo.td:

def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;

These two pieces of information is used by tablegen to generate this array in $(LLVM_ROOT)/build/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc:

static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 0, 0, 0, VTLists+13 },    // EXCEPT_REF
  { 32, 32, 32, VTLists+0 },    // I32
  { 32, 32, 32, VTLists+4 },    // F32
  { 64, 64, 64, VTLists+2 },    // I64
  { 64, 64, 64, VTLists+6 },    // F64
  { 128, 128, 128, VTLists+8 },    // V128
};

There is a line for each register class in this array. There are three zeros in the first line for EXCEPT_REF register class. First two zeros come from case ExceptRef: return 0; here and the third zero is from that def EXCEPT_REF : ... line from lib/Target/WebAssembly/WebAssemblyRegisterInfo.td. Each line makes up an instance of [[ https://github.com/llvm-mirror/llvm/blob/587a2e31eca58dbc0a7535c70aa3bbbb5cfe733c/include/llvm/CodeGen/TargetRegisterInfo.h#L224-L227 | TargetRegisterInfo::RegClassInfo ]].

So these 0s become RegSize, SpillSize, and SpillAlignment member variables in [[ https://github.com/llvm-mirror/llvm/blob/587a2e31eca58dbc0a7535c70aa3bbbb5cfe733c/include/llvm/CodeGen/TargetRegisterInfo.h#L224-L227 | TargetRegisterInfo::RegClassInfo ]] class. But in wasm we don't use this kind of size information anywhere because we don't use physical registers or run register allocation pass.

[aheejin]

• rebase

[dschuff]

Everything else seems pretty straightforward.

include/llvm/CodeGen/MachineValueType.h

751 ↗

(On Diff #136487)

Hm yeah I guess that makes sense and we are already weird when it comes to spilling (we don't). It seems like the other common case it's used for is getting sub/super registers (which we also don't need, but there's target-independent code) and debug info. Hopefully that won't be an issue since they can't be written to memory. Seems like 0 should be ok for now since it's more likely to expose any issues quickly compared to picking a number. But regardless of what we pick here we'll probably be revisiting this issue again.

llvm/trunk/include/llvm/BinaryFormat/Wasm.h

 
 // Type immediate encodings used in various contexts.
 enum : unsigned {
   WASM_TYPE_I32 = 0x7F,
   WASM_TYPE_I64 = 0x7E,
   WASM_TYPE_F32 = 0x7D,
   WASM_TYPE_F64 = 0x7C,
   WASM_TYPE_ANYFUNC = 0x70,
+  WASM_TYPE_EXCEPT_REF = 0x68,
   WASM_TYPE_FUNC = 0x60,
   WASM_TYPE_NORESULT = 0x40, // for blocks with no result values
 };
 
 // Kinds of externals (for imports and exports).
 enum : unsigned {
   WASM_EXTERNAL_FUNCTION = 0x0,
   WASM_EXTERNAL_TABLE = 0x1,

 };
 
 // Subset of types that a value can have
 enum class ValType {
   I32 = WASM_TYPE_I32,
   I64 = WASM_TYPE_I64,
   F32 = WASM_TYPE_F32,
   F64 = WASM_TYPE_F64,
+  EXCEPT_REF = WASM_TYPE_EXCEPT_REF,
 };
 
 // Kind codes used in the custom "name" section
 enum : unsigned {
   WASM_NAMES_FUNCTION = 0x1,
   WASM_NAMES_LOCAL    = 0x2,
 };
 

llvm/trunk/include/llvm/CodeGen/MachineValueType.h

enum SimpleValueType : uint8_t {
       Glue           =  110,   // This glues nodes together during pre-RA sched
 
       isVoid         =  111,   // This has no value
 
       Untyped        =  112,   // This value takes a register, but has
                                // unspecified type.  The register class
                                // will be determined by the opcode.
 
+      ExceptRef      = 113,    // WebAssembly's except_ref type
+
       FIRST_VALUETYPE = 1,     // This is always the beginning of the list.
-      LAST_VALUETYPE =  113,   // This always remains at the end of the list.
+      LAST_VALUETYPE =  114,   // This always remains at the end of the list.
 
       // This is the current maximum for LAST_VALUETYPE.
       // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
       // This value must be a multiple of 32.
       MAX_ALLOWED_VALUETYPE = 128,
 
       // A value of type llvm::TokenTy
       token          = 248,
unsigned getSizeInBits() const {
       case v16i64:
       case nxv32i32:
       case nxv16i64: return 1024;
       case v256i8:
       case v128i16:
       case v64i32:
       case v32i64:
       case nxv32i64: return 2048;
+      case ExceptRef: return 0; // opaque type
       }
     }
 
     unsigned getScalarSizeInBits() const {
       return getScalarType().getSizeInBits();
     }
 
     /// Return the number of bytes overwritten by a store of the specified value

llvm/trunk/include/llvm/CodeGen/ValueTypes.td

 def nxv2f64  : ValueType<128, 106>; // n x  2 x f64 vector value
 def nxv4f64  : ValueType<256, 107>; // n x  4 x f64 vector value
 def nxv8f64  : ValueType<512, 108>; // n x  8 x f64 vector value
 
 def x86mmx : ValueType<64 , 109>;   // X86 MMX value
 def FlagVT : ValueType<0  , 110>;   // Pre-RA sched glue
 def isVoid : ValueType<0  , 111>;   // Produces no value
 def untyped: ValueType<8  , 112>;   // Produces an untyped value
+def ExceptRef: ValueType<0, 113>;   // WebAssembly's except_ref type
 def token  : ValueType<0  , 248>;   // TokenTy
 def MetadataVT: ValueType<0, 249>;  // Metadata
 
 // Pseudo valuetype mapped to the current pointer size to any address space.
 // Should only be used in TableGen.
 def iPTRAny   : ValueType<0, 250>;
 
 // Pseudo valuetype to represent "vector of any size"

llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI,
   case WebAssembly::ExprType::F64: O << "f64"; break;
   case WebAssembly::ExprType::I8x16: O << "i8x16"; break;
   case WebAssembly::ExprType::I16x8: O << "i16x8"; break;
   case WebAssembly::ExprType::I32x4: O << "i32x4"; break;
   case WebAssembly::ExprType::F32x4: O << "f32x4"; break;
   case WebAssembly::ExprType::B8x16: O << "b8x16"; break;
   case WebAssembly::ExprType::B16x8: O << "b16x8"; break;
   case WebAssembly::ExprType::B32x4: O << "b32x4"; break;
+  case WebAssembly::ExprType::ExceptRef: O << "except_ref"; break;
   }
 }
 
 const char *llvm::WebAssembly::TypeToString(MVT Ty) {
   switch (Ty.SimpleTy) {
   case MVT::i32:
     return "i32";
   case MVT::i64:
     return "i64";
   case MVT::f32:
     return "f32";
   case MVT::f64:
     return "f64";
   case MVT::v16i8:
   case MVT::v8i16:
   case MVT::v4i32:
   case MVT::v4f32:
     return "v128";
+  case MVT::ExceptRef:
+    return "except_ref";
   default:
     llvm_unreachable("unsupported type");
   }
 }
 
 const char *llvm::WebAssembly::TypeToString(wasm::ValType Type) {
   switch (Type) {
   case wasm::ValType::I32:
     return "i32";
   case wasm::ValType::I64:
     return "i64";
   case wasm::ValType::F32:
     return "f32";
   case wasm::ValType::F64:
     return "f64";
+  case wasm::ValType::EXCEPT_REF:
+    return "except_ref";
   }
   llvm_unreachable("unsupported type");
 }

llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

 static const unsigned StoreAddressOperandNo = 2;
 
 /// The operand number of the load or store p2align in load/store instructions.
 static const unsigned LoadP2AlignOperandNo = 1;
 static const unsigned StoreP2AlignOperandNo = 0;
 
 /// This is used to indicate block signatures.
 enum class ExprType : unsigned {
-  Void    = 0x40,
-  I32     = 0x7F,
-  I64     = 0x7E,
-  F32     = 0x7D,
-  F64     = 0x7C,
-  I8x16   = 0x7B,
-  I16x8   = 0x7A,
-  I32x4   = 0x79,
-  F32x4   = 0x78,
-  B8x16   = 0x77,
-  B16x8   = 0x76,
-  B32x4   = 0x75
+  Void      = 0x40,
+  I32       = 0x7F,
+  I64       = 0x7E,
+  F32       = 0x7D,
+  F64       = 0x7C,
+  I8x16     = 0x7B,
+  I16x8     = 0x7A,
+  I32x4     = 0x79,
+  F32x4     = 0x78,
+  B8x16     = 0x77,
+  B16x8     = 0x76,
+  B32x4     = 0x75,
+  ExceptRef = 0x68
 };
 
 /// Instruction opcodes emitted via means other than CodeGen.
 static const unsigned Nop = 0x01;
 static const unsigned End = 0x0b;
 
 wasm::ValType toValType(const MVT &Ty);
 
 } // end namespace WebAssembly
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

 }
 
 wasm::ValType WebAssembly::toValType(const MVT &Ty) {
   switch (Ty.SimpleTy) {
   case MVT::i32: return wasm::ValType::I32;
   case MVT::i64: return wasm::ValType::I64;
   case MVT::f32: return wasm::ValType::F32;
   case MVT::f64: return wasm::ValType::F64;
+  case MVT::ExceptRef: return wasm::ValType::EXCEPT_REF;
   default: llvm_unreachable("unexpected type");
   }
 }

llvm/trunk/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

static void FixEndsAtEndOfFunction(
   case MVT::i32: retType = WebAssembly::ExprType::I32; break;
   case MVT::i64: retType = WebAssembly::ExprType::I64; break;
   case MVT::f32: retType = WebAssembly::ExprType::F32; break;
   case MVT::f64: retType = WebAssembly::ExprType::F64; break;
   case MVT::v16i8: retType = WebAssembly::ExprType::I8x16; break;
   case MVT::v8i16: retType = WebAssembly::ExprType::I16x8; break;
   case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;
   case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;
+  case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
   default: llvm_unreachable("unexpected return type");
   }
 
   for (MachineBasicBlock &MBB : reverse(MF)) {
     for (MachineInstr &MI : reverse(MBB)) {
       if (MI.isPosition() || MI.isDebugValue())
         continue;
       if (MI.getOpcode() == WebAssembly::END_BLOCK) {

llvm/trunk/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

static unsigned getDropOpcode(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I64RegClass)
     return WebAssembly::DROP_I64;
   if (RC == &WebAssembly::F32RegClass)
     return WebAssembly::DROP_F32;
   if (RC == &WebAssembly::F64RegClass)
     return WebAssembly::DROP_F64;
   if (RC == &WebAssembly::V128RegClass)
     return WebAssembly::DROP_V128;
+  if (RC == &WebAssembly::EXCEPT_REFRegClass)
+    return WebAssembly::DROP_EXCEPT_REF;
   llvm_unreachable("Unexpected register class");
 }
 
 /// Get the appropriate get_local opcode for the given register class.
 static unsigned getGetLocalOpcode(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I32RegClass)
     return WebAssembly::GET_LOCAL_I32;
   if (RC == &WebAssembly::I64RegClass)
     return WebAssembly::GET_LOCAL_I64;
   if (RC == &WebAssembly::F32RegClass)
     return WebAssembly::GET_LOCAL_F32;
   if (RC == &WebAssembly::F64RegClass)
     return WebAssembly::GET_LOCAL_F64;
   if (RC == &WebAssembly::V128RegClass)
     return WebAssembly::GET_LOCAL_V128;
+  if (RC == &WebAssembly::EXCEPT_REFRegClass)
+    return WebAssembly::GET_LOCAL_EXCEPT_REF;
   llvm_unreachable("Unexpected register class");
 }
 
 /// Get the appropriate set_local opcode for the given register class.
 static unsigned getSetLocalOpcode(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I32RegClass)
     return WebAssembly::SET_LOCAL_I32;
   if (RC == &WebAssembly::I64RegClass)
     return WebAssembly::SET_LOCAL_I64;
   if (RC == &WebAssembly::F32RegClass)
     return WebAssembly::SET_LOCAL_F32;
   if (RC == &WebAssembly::F64RegClass)
     return WebAssembly::SET_LOCAL_F64;
   if (RC == &WebAssembly::V128RegClass)
     return WebAssembly::SET_LOCAL_V128;
+  if (RC == &WebAssembly::EXCEPT_REFRegClass)
+    return WebAssembly::SET_LOCAL_EXCEPT_REF;
   llvm_unreachable("Unexpected register class");
 }
 
 /// Get the appropriate tee_local opcode for the given register class.
 static unsigned getTeeLocalOpcode(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I32RegClass)
     return WebAssembly::TEE_LOCAL_I32;
   if (RC == &WebAssembly::I64RegClass)
     return WebAssembly::TEE_LOCAL_I64;
   if (RC == &WebAssembly::F32RegClass)
     return WebAssembly::TEE_LOCAL_F32;
   if (RC == &WebAssembly::F64RegClass)
     return WebAssembly::TEE_LOCAL_F64;
   if (RC == &WebAssembly::V128RegClass)
     return WebAssembly::TEE_LOCAL_V128;
+  if (RC == &WebAssembly::EXCEPT_REFRegClass)
+    return WebAssembly::TEE_LOCAL_EXCEPT_REF;
   llvm_unreachable("Unexpected register class");
 }
 
 /// Get the type associated with the given register class.
 static MVT typeForRegClass(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I32RegClass)
     return MVT::i32;
   if (RC == &WebAssembly::I64RegClass)
     return MVT::i64;
   if (RC == &WebAssembly::F32RegClass)
     return MVT::f32;
   if (RC == &WebAssembly::F64RegClass)
     return MVT::f64;
+  if (RC == &WebAssembly::EXCEPT_REFRegClass)
+    return MVT::ExceptRef;
   llvm_unreachable("unrecognized register class");
 }
 
 /// Given a MachineOperand of a stackified vreg, return the instruction at the
 /// start of the expression tree.
 static MachineInstr *FindStartOfTree(MachineOperand &MO,
                                      MachineRegisterInfo &MRI,
                                      WebAssemblyFunctionInfo &MFI) {

llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
     case MVT::i1:
     case MVT::i8:
     case MVT::i16:
       return MVT::i32;
     case MVT::i32:
     case MVT::i64:
     case MVT::f32:
     case MVT::f64:
+    case MVT::ExceptRef:
       return VT;
     case MVT::f16:
       return MVT::f32;
     case MVT::v16i8:
     case MVT::v8i16:
     case MVT::v4i32:
     case MVT::v4f32:
       if (Subtarget->hasSIMD128())
for (auto const &Arg : F->args()) {
     case MVT::v4i32:
       Opc = WebAssembly::ARGUMENT_v4i32;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v4f32:
       Opc = WebAssembly::ARGUMENT_v4f32;
       RC = &WebAssembly::V128RegClass;
       break;
+    case MVT::ExceptRef:
+      Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
+      RC = &WebAssembly::EXCEPT_REFRegClass;
+      break;
     default:
       return false;
     }
     unsigned ResultReg = createResultReg(RC);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
       .addImm(i);
     updateValueMap(&Arg, ResultReg);
 
case MVT::v4i32:
           IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::PCALL_INDIRECT_v4i32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v4f32:
       Opc =
           IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
+    case MVT::ExceptRef:
+      Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
+                     : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
+      ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
+      break;
     default:
       return false;
     }
   }
 
   SmallVector<unsigned, 8> Args;
   for (unsigned i = 0, e = Call->getNumArgOperands(); i < e; ++i) {
     Value *V = Call->getArgOperand(i);
bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
   case MVT::f32:
     Opc = WebAssembly::SELECT_F32;
     RC = &WebAssembly::F32RegClass;
     break;
   case MVT::f64:
     Opc = WebAssembly::SELECT_F64;
     RC = &WebAssembly::F64RegClass;
     break;
+  case MVT::ExceptRef:
+    Opc = WebAssembly::SELECT_EXCEPT_REF;
+    RC = &WebAssembly::EXCEPT_REFRegClass;
+    break;
   default:
     return false;
   }
 
   unsigned ResultReg = createResultReg(RC);
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
     .addReg(TrueReg)
     .addReg(FalseReg)
case MVT::v8i16:
     Opc = WebAssembly::RETURN_v8i16;
     break;
   case MVT::v4i32:
     Opc = WebAssembly::RETURN_v4i32;
     break;
   case MVT::v4f32:
     Opc = WebAssembly::RETURN_v4f32;
     break;
+  case MVT::ExceptRef:
+    Opc = WebAssembly::RETURN_EXCEPT_REF;
+    break;
   default: return false;
   }
 
   unsigned Reg;
   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
     Reg = getRegForSignedValue(RV);
   else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
     Reg = getRegForUnsignedValue(RV);

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrCall.td

def CALL_INDIRECT_#vt : SIMD_I<(outs V128:$dst),
                                   0x11>;
 }
 
 let Uses = [SP32, SP64], isCall = 1 in {
   defm : CALL<I32, "i32.">;
   defm : CALL<I64, "i64.">;
   defm : CALL<F32, "f32.">;
   defm : CALL<F64, "f64.">;
+  defm : CALL<EXCEPT_REF, "except_ref.">;
   defm : SIMD_CALL<v16i8, "i8x16.">;
   defm : SIMD_CALL<v8i16, "i16x8.">;
   defm : SIMD_CALL<v4i32, "i32x4.">;
   defm : SIMD_CALL<v4f32, "f32x4.">;
 
   def CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
                     [(WebAssemblycall0 (i32 imm:$callee))],
                     "call    \t$callee", 0x10>;

 def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v16i8 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v8i16 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v4f32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(ExceptRef
+           (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
+          (CALL_EXCEPT_REF tglobaladdr:$callee)>;
 def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
           (CALL_VOID tglobaladdr:$callee)>;
 
 // Patterns for matching a direct call to an external symbol.
 def : Pat<(i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_I32 texternalsym:$callee)>;
 def : Pat<(i64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_I64 texternalsym:$callee)>;
 def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_F32 texternalsym:$callee)>;
 def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_F64 texternalsym:$callee)>;
 def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v16i8 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v8i16 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v4i32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v4f32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(ExceptRef
+           (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
+          (CALL_EXCEPT_REF texternalsym:$callee)>;
 def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
           (CALL_VOID texternalsym:$callee)>;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td

 
 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
 
 let isReturn = 1 in {
   defm : RETURN<I32>;
   defm : RETURN<I64>;
   defm : RETURN<F32>;
   defm : RETURN<F64>;
+  defm : RETURN<EXCEPT_REF>;
   defm : SIMD_RETURN<v16i8>;
   defm : SIMD_RETURN<v8i16>;
   defm : SIMD_RETURN<v4i32>;
   defm : SIMD_RETURN<v4f32>;
 
   def RETURN_VOID : I<(outs), (ins), [(WebAssemblyreturn)], "return", 0x0f>;
 
   // This is to RETURN_VOID what FALLTHROUGH_RETURN_#vt is to RETURN_#vt.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrExceptRef.td

+// WebAssemblyInstrExceptRef.td-WebAssembly except_ref codegen --*- tablegen -*-
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief WebAssembly except_ref operand code-gen constructs.
+///
+//===----------------------------------------------------------------------===//
+
+let Defs = [ARGUMENTS] in {
+
+def SELECT_EXCEPT_REF : I<(outs EXCEPT_REF:$dst),
+                          (ins EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond),
+                          [(set EXCEPT_REF:$dst,
+                           (select I32:$cond, EXCEPT_REF:$lhs,
+                            EXCEPT_REF:$rhs))],
+                          "except_ref.select\t$dst, $lhs, $rhs, $cond", 0x1b>;
+
+} // Defs = [ARGUMENTS]
+
+def : Pat<(select (i32 (setne I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
+          (SELECT_EXCEPT_REF EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond)>;
+def : Pat<(select (i32 (seteq I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
+          (SELECT_EXCEPT_REF EXCEPT_REF:$rhs, EXCEPT_REF:$lhs, I32:$cond)>;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

multiclass SIMD_ARGUMENT<ValueType vt> {
   def ARGUMENT_#vt : SIMD_I<(outs V128:$res), (ins i32imm:$argno),
                             [(set (vt V128:$res),
                                   (WebAssemblyargument timm:$argno))]>;
 }
 defm : ARGUMENT<I32>;
 defm : ARGUMENT<I64>;
 defm : ARGUMENT<F32>;
 defm : ARGUMENT<F64>;
+defm : ARGUMENT<EXCEPT_REF>;
 defm : SIMD_ARGUMENT<v16i8>;
 defm : SIMD_ARGUMENT<v8i16>;
 defm : SIMD_ARGUMENT<v4i32>;
 defm : SIMD_ARGUMENT<v4f32>;
 
 let Defs = [ARGUMENTS] in {
 
 // get_local and set_local are not generated by instruction selection; they

 
 } // hasSideEffects = 0
 }
 defm : LOCAL<I32>;
 defm : LOCAL<I64>;
 defm : LOCAL<F32>;
 defm : LOCAL<F64>;
 defm : LOCAL<V128>, Requires<[HasSIMD128]>;
+defm : LOCAL<EXCEPT_REF>, Requires<[HasExceptionHandling]>;
 
 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
 def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
                   [(set I32:$res, imm:$imm)],
                   "i32.const\t$res, $imm", 0x41>;
 def CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
                   [(set I64:$res, imm:$imm)],
                   "i64.const\t$res, $imm", 0x42>;

 include "WebAssemblyInstrMemory.td"
 include "WebAssemblyInstrCall.td"
 include "WebAssemblyInstrControl.td"
 include "WebAssemblyInstrInteger.td"
 include "WebAssemblyInstrConv.td"
 include "WebAssemblyInstrFloat.td"
 include "WebAssemblyInstrAtomics.td"
 include "WebAssemblyInstrSIMD.td"
+include "WebAssemblyInstrExceptRef.td"

llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

 def SP32 : WebAssemblyReg<"%SP32">;
 def SP64 : WebAssemblyReg<"%SP64">;
 
 // The register allocation framework requires register classes have at least
 // one register, so we define a few for the floating point register classes
 // since we otherwise don't need a physical register in those classes.
 def F32_0 : WebAssemblyReg<"%f32.0">;
 def F64_0 : WebAssemblyReg<"%f64.0">;
-
 def V128_0: WebAssemblyReg<"%v128">;
+def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">;
 
 // The value stack "register". This is an opaque entity which serves to order
 // uses and defs that must remain in LIFO order.
 def VALUE_STACK : WebAssemblyReg<"STACK">;
 
 // The incoming arguments "register". This is an opaque entity which serves to
 // order the ARGUMENT instructions that are emulating live-in registers and
 // must not be scheduled below other instructions.
 def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">;
 
 //===----------------------------------------------------------------------===//
 //  Register classes
 //===----------------------------------------------------------------------===//
 
 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
 def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
 def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
-
+def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;

llvm/trunk/utils/TableGen/CodeGenTarget.cpp

StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::nxv2f64:  return "MVT::nxv2f64";
   case MVT::nxv4f64:  return "MVT::nxv4f64";
   case MVT::nxv8f64:  return "MVT::nxv8f64";
   case MVT::token:    return "MVT::token";
   case MVT::Metadata: return "MVT::Metadata";
   case MVT::iPTR:     return "MVT::iPTR";
   case MVT::iPTRAny:  return "MVT::iPTRAny";
   case MVT::Untyped:  return "MVT::Untyped";
+  case MVT::ExceptRef: return "MVT::ExceptRef";
   default: llvm_unreachable("ILLEGAL VALUE TYPE!");
   }
 }
 
 /// getQualifiedName - Return the name of the specified record, with a
 /// namespace qualifier if the record contains one.
 ///
 std::string llvm::getQualifiedName(const Record *R) {