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[WebAssembly] Add except_ref as a first-class type
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Authored by aheejin on Feb 23 2018, 5:50 PM.

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aheejin created this revision.Feb 23 2018, 5:50 PM
aheejin updated this revision to Diff 136487.Mar 1 2018, 2:53 AM
  • Opcode for except_ref has changed to -0x18
dschuff added inline comments.Mar 1 2018, 3:10 PM
include/llvm/CodeGen/MachineValueType.h
751 ↗(On Diff #136487)

This seems fishy. What would a caller actually do with a 0-size type? Do we expect this to ever be called? Should it be an unreachable instead?

aheejin updated this revision to Diff 136680.EditedMar 1 2018, 11:07 PM

rebase + change -0x18 to 0x68 to use uint8_t

aheejin updated this revision to Diff 136689.Mar 2 2018, 12:43 AM
  • deleted , at the end to match the previous code
aheejin added inline comments.Mar 2 2018, 3:36 AM
include/llvm/CodeGen/MachineValueType.h
751 ↗(On Diff #136487)

Yes, it is called here, while tablegen generates tables. We need this line, because if it's an unreachable, it will crash the LLVM build while running tablegen.

Also we have one more 0 in this CL in this line in lib/Target/WebAssembly/WebAssemblyRegisterInfo.td:

def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;

These two pieces of information is used by tablegen to generate this array in $(LLVM_ROOT)/build/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc:

static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 0, 0, 0, VTLists+13 },    // EXCEPT_REF
  { 32, 32, 32, VTLists+0 },    // I32
  { 32, 32, 32, VTLists+4 },    // F32
  { 64, 64, 64, VTLists+2 },    // I64
  { 64, 64, 64, VTLists+6 },    // F64
  { 128, 128, 128, VTLists+8 },    // V128
};

There is a line for each register class in this array. There are three zeros in the first line for EXCEPT_REF register class. First two zeros come from case ExceptRef: return 0; here and the third zero is from that def EXCEPT_REF : ... line from lib/Target/WebAssembly/WebAssemblyRegisterInfo.td. Each line makes up an instance of TargetRegisterInfo::RegClassInfo.

So these 0s become RegSize, SpillSize, and SpillAlignment member variables in TargetRegisterInfo::RegClassInfo class. But in wasm we don't use this kind of size information anywhere because we don't use physical registers or run register allocation pass.

aheejin updated this revision to Diff 136887.Mar 2 2018, 5:07 PM
  • rebase

Everything else seems pretty straightforward.

include/llvm/CodeGen/MachineValueType.h
751 ↗(On Diff #136487)

Hm yeah I guess that makes sense and we are already weird when it comes to spilling (we don't). It seems like the other common case it's used for is getting sub/super registers (which we also don't need, but there's target-independent code) and debug info. Hopefully that won't be an issue since they can't be written to memory. Seems like 0 should be ok for now since it's more likely to expose any issues quickly compared to picking a number. But regardless of what we pick here we'll probably be revisiting this issue again.

dschuff accepted this revision.Mar 7 2018, 4:52 PM
This revision is now accepted and ready to land.Mar 7 2018, 4:52 PM
This revision was automatically updated to reflect the committed changes.