[AArch64] Add support for secrel add/load/store relocations for COFF

[mstorsjo]

Summary

The new symbol variants :secrel_lo12: and :secrel_hi12: aren't something that is in use anywhere else, but they seem to be a straightforward enough match to existing concepts.

This adds a new flag VK_SECREL in AArch64MCExpr, but to have this flag fall under the VK_SymLocBits bit mask, I had to make the mask VK_SymLocBits non-contiguous, to avoid having to renumber the rest of the enum.

[mstorsjo]

Added documentation about the new symbol variants.

[mstorsjo]

@compnerd wanted some more opinions on this from @rnk and @majnemer. He also wanted to make sure that the new relocations are forbidden if targeting ELF; this already happens, e.g. like this:

test.s:2:2: error: invalid fixup for 64-bit load/store instruction

ldr x0, [x0, :secrel_lo12:foo]

These aren't strictly necessary to expose on the assembler level in order to implement the next step (actually supporting native TLS), but having them supported in the assembler is useful for testing and for completeness sake.

[rnk]

Looks good to me, but I don't know much about AArch64 or its COFF relocations.

lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h

38–39 ↗

(On Diff #135320)

VariantKind has 32 bits. It's probably cleaner to move the VK_AddressFragBits over to 0xf00 and VK_NC to 0x1000 and give ourselves 8 bits for symbol locations.

lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp

71–72 ↗

(On Diff #135320)

This is outside the scope of the change, but we really should invent a separate 16 bit section index fixup for COFF instead of overloading this 2 byte secrel fixup for section table indices.

[mstorsjo]

lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h

38–39 ↗

(On Diff #135320)

Actually, I don't know what I was thinking here, I could just make VK_SECREL = 0x008 which fits within the existing mask as well. Will commit with that simplification.

llvm/trunk/docs/Extensions.rst

MC supports these flags in the COFF ``.section`` directive:
   - ``y``: Not readable
   - ``D``: Discardable (``IMAGE_SCN_MEM_DISCARDABLE``)
 
 These flags are all compatible with gas, with the exception of the ``D`` flag,
 which gnu as does not support. For gas compatibility, sections with a name
 starting with ".debug" are implicitly discardable.
 
 
+ARM64/COFF-Dependent
+--------------------
+
+Relocations
+^^^^^^^^^^^
+
+The following additional symbol variants are supported:
+
+**:secrel_lo12:** generates a relocation that corresponds to the COFF relocation
+types ``IMAGE_REL_ARM64_SECREL_LOW12A`` or ``IMAGE_REL_ARM64_SECREL_LOW12L``.
+
+**:secrel_hi12:** generates a relocation that corresponds to the COFF relocation
+type ``IMAGE_REL_ARM64_SECREL_HIGH12A``.
+
+.. code-block:: gas
+
+    add x0, x0, :secrel_hi12:symbol
+    ldr x0, [x0, :secrel_lo12:symbol]
+
+    add x1, x1, :secrel_hi12:symbol
+    add x1, x1, :secrel_lo12:symbol
+    ...
+
+
 ELF-Dependent
 -------------
 
 ``.section`` Directive
 ^^^^^^^^^^^^^^^^^^^^^^
 
 In order to support creating multiple sections with the same name and comdat,
 it is possible to add an unique number at the end of the ``.seciton`` directive.

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const {
     if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
         ELFRefKind == AArch64MCExpr::VK_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_GOT_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC ||
         ELFRefKind == AArch64MCExpr::VK_TPREL_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
         ELFRefKind == AArch64MCExpr::VK_GOTTPREL_LO12_NC ||
-        ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12) {
+        ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
+        ELFRefKind == AArch64MCExpr::VK_SECREL_LO12 ||
+        ELFRefKind == AArch64MCExpr::VK_SECREL_HI12) {
       // Note that we don't range-check the addend. It's adjusted modulo page
       // size when converted, so there is no "out of range" condition when using
       // @pageoff.
       return Addend >= 0 && (Addend % Scale) == 0;
     } else if (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF ||
                DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) {
       // @gotpageoff/@tlvppageoff can only be used directly, not with an addend.
       return Addend == 0;
if (AArch64AsmParser::classifySymbolRef(Expr, ELFRefKind,
           || (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF && Addend == 0)
           || ELFRefKind == AArch64MCExpr::VK_LO12
           || ELFRefKind == AArch64MCExpr::VK_DTPREL_HI12
           || ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12
           || ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC
           || ELFRefKind == AArch64MCExpr::VK_TPREL_HI12
           || ELFRefKind == AArch64MCExpr::VK_TPREL_LO12
           || ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC
-          || ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12;
+          || ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12
+          || ELFRefKind == AArch64MCExpr::VK_SECREL_HI12
+          || ELFRefKind == AArch64MCExpr::VK_SECREL_LO12;
     }
 
     // If it's a constant, it should be a real immediate in range:
     if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
       return CE->getValue() >= 0 && CE->getValue() <= 0xfff;
 
     // If it's an expression, we hope for the best and let the fixup/relocation
     // code deal with it.
RefKind = StringSwitch<AArch64MCExpr::VariantKind>(LowerCase)
                   .Case("tlsdesc_lo12", AArch64MCExpr::VK_TLSDESC_LO12)
                   .Case("got", AArch64MCExpr::VK_GOT_PAGE)
                   .Case("got_lo12", AArch64MCExpr::VK_GOT_LO12)
                   .Case("gottprel", AArch64MCExpr::VK_GOTTPREL_PAGE)
                   .Case("gottprel_lo12", AArch64MCExpr::VK_GOTTPREL_LO12_NC)
                   .Case("gottprel_g1", AArch64MCExpr::VK_GOTTPREL_G1)
                   .Case("gottprel_g0_nc", AArch64MCExpr::VK_GOTTPREL_G0_NC)
                   .Case("tlsdesc", AArch64MCExpr::VK_TLSDESC_PAGE)
+                  .Case("secrel_lo12", AArch64MCExpr::VK_SECREL_LO12)
+                  .Case("secrel_hi12", AArch64MCExpr::VK_SECREL_HI12)
                   .Default(AArch64MCExpr::VK_INVALID);
 
     if (RefKind == AArch64MCExpr::VK_INVALID)
       return TokError("expect relocation specifier in operand after ':'");
 
     Parser.Lex(); // Eat identifier
 
     if (parseToken(AsmToken::Colon, "expect ':' after relocation specifier"))
if (Inst.getOperand(2).isExpr()) {
         // Only allow these with ADDXri/ADDWri
         if ((ELFRefKind == AArch64MCExpr::VK_LO12 ||
              ELFRefKind == AArch64MCExpr::VK_DTPREL_HI12 ||
              ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12 ||
              ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC ||
              ELFRefKind == AArch64MCExpr::VK_TPREL_HI12 ||
              ELFRefKind == AArch64MCExpr::VK_TPREL_LO12 ||
              ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
-             ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12) &&
+             ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
+             ELFRefKind == AArch64MCExpr::VK_SECREL_LO12 ||
+             ELFRefKind == AArch64MCExpr::VK_SECREL_HI12) &&
             (Inst.getOpcode() == AArch64::ADDXri ||
              Inst.getOpcode() == AArch64::ADDWri))
           return false;
 
         // Don't allow symbol refs in the immediate field otherwise
         // Note: Loc.back() may be Loc[1] or Loc[2] depending on the number of
         // operands of the original instruction (i.e. 'add w0, w1, borked' vs
         // 'cmp w0, 'borked')

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
 
   ++MCNumFixups;
 
   // Set the shift bit of the add instruction for relocation types
   // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
   if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
     AArch64MCExpr::VariantKind RefKind = A64E->getKind();
     if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
-        RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+        RefKind == AArch64MCExpr::VK_DTPREL_HI12 ||
+        RefKind == AArch64MCExpr::VK_SECREL_HI12)
       ShiftVal = 12;
   }
   return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 
 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
 /// branch target.
 uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h

enum VariantKind {
     // symbol. E.g. direct, via the GOT, ...
     VK_ABS      = 0x001,
     VK_SABS     = 0x002,
     VK_GOT      = 0x003,
     VK_DTPREL   = 0x004,
     VK_GOTTPREL = 0x005,
     VK_TPREL    = 0x006,
     VK_TLSDESC  = 0x007,
+    VK_SECREL   = 0x008,
     VK_SymLocBits = 0x00f,
 
     // Variants specifying which part of the final address calculation is
     // used. E.g. the low 12 bits for an ADD/LDR, the middle 16 bits for a
     // MOVZ/MOVK.
     VK_PAGE     = 0x010,
     VK_PAGEOFF  = 0x020,
     VK_HI12     = 0x030,
enum VariantKind {
     VK_TPREL_G1_NC       = VK_TPREL    | VK_G1      | VK_NC,
     VK_TPREL_G0          = VK_TPREL    | VK_G0,
     VK_TPREL_G0_NC       = VK_TPREL    | VK_G0      | VK_NC,
     VK_TPREL_HI12        = VK_TPREL    | VK_HI12,
     VK_TPREL_LO12        = VK_TPREL    | VK_PAGEOFF,
     VK_TPREL_LO12_NC     = VK_TPREL    | VK_PAGEOFF | VK_NC,
     VK_TLSDESC_LO12      = VK_TLSDESC  | VK_PAGEOFF,
     VK_TLSDESC_PAGE      = VK_TLSDESC  | VK_PAGE,
+    VK_SECREL_LO12       = VK_SECREL   | VK_PAGEOFF,
+    VK_SECREL_HI12       = VK_SECREL   | VK_HI12,
 
     VK_INVALID  = 0xfff
   };
 
 private:
   const MCExpr *Expr;
   const VariantKind Kind;
 

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp

StringRef AArch64MCExpr::getVariantKindName() const {
   case VK_GOT_PAGE:            return ":got:";
   case VK_GOT_LO12:            return ":got_lo12:";
   case VK_GOTTPREL_PAGE:       return ":gottprel:";
   case VK_GOTTPREL_LO12_NC:    return ":gottprel_lo12:";
   case VK_GOTTPREL_G1:         return ":gottprel_g1:";
   case VK_GOTTPREL_G0_NC:      return ":gottprel_g0_nc:";
   case VK_TLSDESC:             return "";
   case VK_TLSDESC_PAGE:        return ":tlsdesc:";
+  case VK_SECREL_LO12:         return ":secrel_lo12:";
+  case VK_SECREL_HI12:         return ":secrel_hi12:";
   default:
     llvm_unreachable("Invalid ELF symbol kind");
   }
 }
 
 void AArch64MCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
   if (getKind() != VK_NONE)
     OS << getVariantKindName();

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp

 //= AArch64WinCOFFObjectWriter.cpp - AArch64 Windows COFF Object Writer C++ =//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===---------------------------------------------------------------------===//
 
 #include "MCTargetDesc/AArch64FixupKinds.h"
+#include "MCTargetDesc/AArch64MCExpr.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/COFF.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCValue.h"

 
 } // end anonymous namespace
 
 unsigned AArch64WinCOFFObjectWriter::getRelocType(
     MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup,
     bool IsCrossSection, const MCAsmBackend &MAB) const {
   auto Modifier = Target.isAbsolute() ? MCSymbolRefExpr::VK_None
                                       : Target.getSymA()->getKind();
+  const MCExpr *Expr = Fixup.getValue();
 
   switch (static_cast<unsigned>(Fixup.getKind())) {
   default: {
     const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
     report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
   }
 
   case FK_Data_4:
unsigned AArch64WinCOFFObjectWriter::getRelocType(
 
   case FK_SecRel_2:
     return COFF::IMAGE_REL_ARM64_SECTION;
 
   case FK_SecRel_4:
     return COFF::IMAGE_REL_ARM64_SECREL;
 
   case AArch64::fixup_aarch64_add_imm12:
+    if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
+      AArch64MCExpr::VariantKind RefKind = A64E->getKind();
+      if (RefKind == AArch64MCExpr::VK_SECREL_LO12)
+        return COFF::IMAGE_REL_ARM64_SECREL_LOW12A;
+      if (RefKind == AArch64MCExpr::VK_SECREL_HI12)
+        return COFF::IMAGE_REL_ARM64_SECREL_HIGH12A;
+    }
     return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12A;
 
   case AArch64::fixup_aarch64_ldst_imm12_scale1:
   case AArch64::fixup_aarch64_ldst_imm12_scale2:
   case AArch64::fixup_aarch64_ldst_imm12_scale4:
   case AArch64::fixup_aarch64_ldst_imm12_scale8:
   case AArch64::fixup_aarch64_ldst_imm12_scale16:
+    if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
+      AArch64MCExpr::VariantKind RefKind = A64E->getKind();
+      if (RefKind == AArch64MCExpr::VK_SECREL_LO12)
+        return COFF::IMAGE_REL_ARM64_SECREL_LOW12L;
+    }
     return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12L;
 
   case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     return COFF::IMAGE_REL_ARM64_PAGEBASE_REL21;
 
   case AArch64::fixup_aarch64_pcrel_branch26:
   case AArch64::fixup_aarch64_pcrel_call26:
     return COFF::IMAGE_REL_ARM64_BRANCH26;

llvm/trunk/test/MC/AArch64/coff-relocations.s

 
 .align 2
 adrp x0, baz + 0x12345
 baz:
 add x0, x0, :lo12:foo + 0x12345
 ldrb w0, [x0, :lo12:foo + 0x12345]
 ldr x0, [x0, :lo12:foo + 0x12348]
 
+; IMAGE_REL_ARM64_SECREL_LOW12A
+add x0, x0, :secrel_lo12:foo
+; IMAGE_REL_ARM64_SECREL_HIGH12A
+add x0, x0, :secrel_hi12:foo
+; IMAGE_REL_ARM64_SECREL_LOW12L
+ldr x0, [x0, :secrel_lo12:foo]
+
 ; CHECK: Format: COFF-ARM64
 ; CHECK: Arch: aarch64
 ; CHECK: AddressSize: 64bit
 ; CHECK: Relocations [
 ; CHECK:   Section (1) .text {
 ; CHECK: 0x4 IMAGE_REL_ARM64_ADDR32 foo
 ; CHECK: 0x8 IMAGE_REL_ARM64_ADDR32NB func
 ; CHECK: 0xC IMAGE_REL_ARM64_ADDR64 arr
 ; CHECK: 0x14 IMAGE_REL_ARM64_BRANCH26 target
 ; CHECK: 0x18 IMAGE_REL_ARM64_PAGEBASE_REL21 foo
 ; CHECK: 0x1C IMAGE_REL_ARM64_PAGEOFFSET_12A foo
 ; CHECK: 0x20 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
 ; CHECK: 0x24 IMAGE_REL_ARM64_PAGEBASE_REL21 bar
 ; CHECK: 0x28 IMAGE_REL_ARM64_SECREL .text
 ; CHECK: 0x2C IMAGE_REL_ARM64_SECTION func
 ; CHECK: 0x30 IMAGE_REL_ARM64_PAGEBASE_REL21 baz
 ; CHECK: 0x34 IMAGE_REL_ARM64_PAGEOFFSET_12A foo
 ; CHECK: 0x38 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
 ; CHECK: 0x3C IMAGE_REL_ARM64_PAGEOFFSET_12L foo
+; CHECK: 0x40 IMAGE_REL_ARM64_SECREL_LOW12A foo
+; CHECK: 0x44 IMAGE_REL_ARM64_SECREL_HIGH12A foo
+; CHECK: 0x48 IMAGE_REL_ARM64_SECREL_LOW12L foo
 ; CHECK:   }
 ; CHECK: ]
 
 ; DISASM: 30:       20 1a 09 b0     adrp    x0, #305418240
 ; DISASM: 34:       00 14 0d 91     add     x0, x0, #837
 ; DISASM: 38:       00 14 4d 39     ldrb    w0, [x0, #837]
 ; DISASM: 3c:       00 a4 41 f9     ldr     x0, [x0, #840]
+; DISASM: 40:       00 00 00 91     add     x0, x0, #0
+; DISASM: 44:       00 00 40 91     add     x0, x0, #0, lsl #12
+; DISASM: 48:       00 00 40 f9     ldr     x0, [x0]