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[AMDGPU][MC] Added support of 64-bit image atomics
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Authored by dp on Jan 24 2018, 4:39 AM.

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Summary

See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998

It is not clear if atomics should support dmask=0. Currently only 0x1, 0x3 and 0xf values are allowed. Spec states that "all other values of dmask are illegal".

Depends on D42186

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Repository
rL LLVM

Event Timeline

dp created this revision.Jan 24 2018, 4:39 AM
dp updated this revision to Diff 131232.Jan 24 2018, 5:23 AM

Updated to exclude changes from D42186

artem.tamazov accepted this revision.Jan 25 2018, 7:17 AM
artem.tamazov added inline comments.
test/MC/AMDGPU/mimg.s
37 ↗(On Diff #131232)

Does SP3 supporting this syntax? SP3 docs says that all image_atomic insts have ...vgpr_d[4], vgpr_a..., i.e. 4-dword data and 1-dword address.

This revision is now accepted and ready to land.Jan 25 2018, 7:17 AM
dp added inline comments.Jan 25 2018, 8:13 AM
test/MC/AMDGPU/mimg.s
37 ↗(On Diff #131232)

Available SP3 documentation looks incomplete. Here are a few examples of code I got from SP3 decoder:

// default SP3 dmask is 1
[0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00] image_atomic_add v5, v1, s[92:99] unorm
[0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00] image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm

Also for gfx10 SP3 decoder may generate address with more than 1 dword.

This revision was automatically updated to reflect the committed changes.