[PowerPC] Secure PLT support

[spetrovic]

Summary

This patch supports secure PLT mode for PowerPC 32 architecture. I'm planning to add patch that supports -msecure-plt option in clang also.

[spetrovic]

Updated patch so it covers cases where we have just function call, without global variables as arguments or global variables used within function.

[jhibbits]

test/CodeGen/PowerPC/secure-plt.ll

38

Instead of providing this as NO-SECURE-PLT-NOT, such that you're saying it's *not* generating secure PLT, can you instead check for BSS-PLT, and use the BSS PLT asm? You could put this in the already existing ppc32-pic.ll and ppc32-pic-large.ll

[petarj]

Can we get this patch in?

[jhibbits]

test/CodeGen/PowerPC/ppc32-pic-large.ll

14 ↗

(On Diff #136765)

I meant instead of copying the same code into these two files and getting the same result as I already put in here, have two RUN lines in the ppc32-pic-large.ll/ppc32-pic.ll -- the existing RUN line, and an additional line to test secure-plt.

Then we'd have lines of LARGE-BSS and LARGE-BSS-SECUREPLT, or such.

The change you made here is effectively just duplicating the test I already wrote.

[spetrovic]

test/CodeGen/PowerPC/ppc32-pic-large.ll

14 ↗

(On Diff #136765)

Since this solution doesn't support small pic mode, is it OK just to add secure plt checks in ppc32-pic-large.ll ?

[jhibbits]

test/CodeGen/PowerPC/ppc32-pic-large.ll

14 ↗

(On Diff #136765)

That's fine with me.

[spetrovic]

Is this patch OK to commit now ?

[jhibbits]

Looks fine to me.

[joerg]

It should be kept in mind that secure PLT is desirable for certain cases with non-position independent code as well. Even in static binaries it can be desirable... But that is for a follow-up patch.

include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSGD_HA,   // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,          // symbol@tlsgd
     VK_PPC_GOT_TLSLD,      // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,   // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,   // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,   // symbol@got@tlsld@ha
     VK_PPC_TLSLD,          // symbol@tlsld
     VK_PPC_LOCAL,          // symbol@local
+    VK_PPC_SECURE_PLT,     // symbol+32768@plt
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
 
     VK_Hexagon_PCREL,
     VK_Hexagon_LO16,
     VK_Hexagon_HI16,
     VK_Hexagon_GPREL,
     VK_Hexagon_GD_GOT,

lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_GOTOFF: return "GOTOFF";
   case VK_GOTREL: return "GOTREL";
   case VK_GOTPCREL: return "GOTPCREL";
   case VK_GOTTPOFF: return "GOTTPOFF";
   case VK_INDNTPOFF: return "INDNTPOFF";
   case VK_NTPOFF: return "NTPOFF";
   case VK_GOTNTPOFF: return "GOTNTPOFF";
   case VK_PLT: return "PLT";
+  case VK_PPC_SECURE_PLT: return "PLT";
   case VK_TLSGD: return "TLSGD";
   case VK_TLSLD: return "TLSLD";
   case VK_TLSLDM: return "TLSLDM";
   case VK_TPOFF: return "TPOFF";
   case VK_TPREL: return "TPREL";
   case VK_TLSCALL: return "tlscall";
   case VK_TLSDESC: return "tlsdesc";
   case VK_TLVP: return "TLVP";
return StringSwitch<VariantKind>(Name.lower())
     .Case("rel32@lo", VK_AMDGPU_REL32_LO)
     .Case("rel32@hi", VK_AMDGPU_REL32_HI)
     .Default(VK_Invalid);
 }
 
 void MCSymbolRefExpr::printVariantKind(raw_ostream &OS) const {
   if (UseParensForSymbolVariant)
     OS << '(' << MCSymbolRefExpr::getVariantKindName(getKind()) << ')';
-  else
+  else {
+    if (getKind() == VK_PPC_SECURE_PLT)
+      OS << "+32768";
     OS << '@' << MCSymbolRefExpr::getVariantKindName(getKind());
   }
+}
 
 /* *** */
 
 void MCTargetExpr::anchor() {}
 
 /* *** */
 
 bool MCExpr::evaluateAsAbsolute(int64_t &Res) const {

lib/Target/PowerPC/PPC.td

 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
                                         "Enable Book E instructions",
                                         [FeatureICBT]>;
 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
                               "Has only the msync instruction instead of sync",
                               [FeatureBookE]>;
 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
                                         "Enable E500/E500mc instructions">;
+def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
+                                        "Enable secure plt mode">;
 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
                                         "Enable PPC 4xx instructions">;
 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
                                         "Enable PPC 6xx instructions">;
 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
                                         "Enable QPX instructions",
                                         [FeatureHardFloat]>;
 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",

lib/Target/PowerPC/PPCAsmPrinter.cpp

case PPC::MovePCtoLR8: {
     // Emit the label.
     OutStreamer->EmitLabel(PICBase);
     return;
   }
   case PPC::UpdateGBR: {
     // Transform %rd = UpdateGBR(%rt, %ri)
     // Into: lwz %rt, .L0$poff - .L0$pb(%ri)
     //       add %rd, %rt, %ri
+    // or into (if secure plt mode is on):
+    //       addis r30, r30, .LTOC - .L0$pb@ha
+    //       addi r30, r30, .LTOC - .L0$pb@l
     // Get the offset from the GOT Base Register to the GOT
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
+    if (Subtarget->isSecurePlt() && isPositionIndependent()) {
+      TmpInst.setOpcode(PPC::ADDIS);
+      const MCExpr *Exp =
+          MCSymbolRefExpr::create(OutContext.getOrCreateSymbol(Twine(".LTOC")),
+                                                               OutContext);
+      const MCExpr *PBha =
+        MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
+                                MCSymbolRefExpr::VK_PPC_HA,
+                                OutContext);
+      const MCExpr *PBl =
+        MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
+                                MCSymbolRefExpr::VK_PPC_LO,
+                                OutContext);
+      const MCOperand PICR = TmpInst.getOperand(0);
+
+      TmpInst.getOperand(2) =
+          MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PBha, OutContext));
+      TmpInst.getOperand(0) = PICR;
+      TmpInst.getOperand(1) = PICR;
+      EmitToStreamer(*OutStreamer, TmpInst);
+
+      TmpInst.setOpcode(PPC::ADDI);
+      TmpInst.getOperand(2) =
+          MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PBl, OutContext));
+      TmpInst.getOperand(0) = PICR;
+      TmpInst.getOperand(1) = PICR;
+      EmitToStreamer(*OutStreamer, TmpInst);
+      return;
+    } else {
       MCSymbol *PICOffset =
         MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();
       TmpInst.setOpcode(PPC::LWZ);
       const MCExpr *Exp =
         MCSymbolRefExpr::create(PICOffset, MCSymbolRefExpr::VK_None, OutContext);
       const MCExpr *PB =
         MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
                                 MCSymbolRefExpr::VK_None,
                                 OutContext);
       const MCOperand TR = TmpInst.getOperand(1);
       const MCOperand PICR = TmpInst.getOperand(0);
 
       // Step 1: lwz %rt, .L$poff - .L$pb(%ri)
       TmpInst.getOperand(1) =
           MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PB, OutContext));
       TmpInst.getOperand(0) = TR;
       TmpInst.getOperand(2) = PICR;
       EmitToStreamer(*OutStreamer, TmpInst);
 
       TmpInst.setOpcode(PPC::ADD4);
       TmpInst.getOperand(0) = PICR;
       TmpInst.getOperand(1) = TR;
       TmpInst.getOperand(2) = PICR;
       EmitToStreamer(*OutStreamer, TmpInst);
       return;
     }
+  }
   case PPC::LWZtoc: {
     // Transform %r3 = LWZtoc @min1, %r2
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to LWZ, and the global address operand to be a
     // reference to the GOT entry we will synthesize later.
     TmpInst.setOpcode(PPC::LWZ);
     const MachineOperand &MO = MI->getOperand(1);

lib/Target/PowerPC/PPCMCInstLower.cpp

switch (access) {
     case PPCII::MO_TOC_LO:
       RefKind = MCSymbolRefExpr::VK_PPC_TOC_LO;
       break;
     case PPCII::MO_TLS:
       RefKind = MCSymbolRefExpr::VK_PPC_TLS;
       break;
   }
 
-  if (MO.getTargetFlags() == PPCII::MO_PLT)
+  if (MO.getTargetFlags() == PPCII::MO_PLT) {
+    const MachineFunction *MF = MO.getParent()->getParent()->getParent();
+    const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
+    const TargetMachine &TM = Printer.TM;
+
+    // -msecure-plt option works only in PIC mode.
+    if (Subtarget->isSecurePlt() && TM.isPositionIndependent())
+      RefKind = MCSymbolRefExpr::VK_PPC_SECURE_PLT;
+    else
       RefKind = MCSymbolRefExpr::VK_PLT;
+  }
 
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
 
   if (!MO.isJTI() && MO.getOffset())
     Expr = MCBinaryExpr::createAdd(Expr,
                                    MCConstantExpr::create(MO.getOffset(), Ctx),
                                    Ctx);
 

lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool HasInvariantFunctionDescriptors;
   bool HasPartwordAtomics;
   bool HasDirectMove;
   bool HasHTM;
   bool HasFusion;
   bool HasFloat128;
   bool IsISA3_0;
   bool UseLongCalls;
+  bool SecurePlt;
 
   POPCNTDKind HasPOPCNTD;
 
   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
   /// alignment has not been changed, we need to keep the 16-byte alignment
   /// of the stack.
   bool IsQPXStackUnaligned;
 
public:
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }
   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
   bool isPPC4xx() const { return IsPPC4xx; }
   bool isPPC6xx() const { return IsPPC6xx; }
+  bool isSecurePlt() const {return SecurePlt; }
   bool isE500() const { return IsE500; }
   bool isFeatureMFTB() const { return FeatureMFTB; }
   bool isDeprecatedDST() const { return DeprecatedDST; }
   bool hasICBT() const { return HasICBT; }
   bool hasInvariantFunctionDescriptors() const {
     return HasInvariantFunctionDescriptors;
   }
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }

test/CodeGen/PowerPC/secure-plt.ll

+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -O2 -mattr=+secure-plt -relocation-model=pic %s -o - | FileCheck %s -check-prefix=SECURE-PLT
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -O2 -relocation-model=pic %s -o - | FileCheck %s -check-prefix=NO-SECURE-PLT
+
+@.str = private unnamed_addr constant [14 x i8] c"\0AHello World\0A\00", align 1
+
+define void @foo() {
+entry:
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i32 0, i32 0))
+  ret void
+}
+
+declare i32 @printf(i8*, ...)
+
+; CHECK-LABEL: foo:
+; SECURE-PLT: addis 30, 30, .LTOC-.L0$pb@ha
+; SECURE-PLT: addi 30, 30, .LTOC-.L0$pb@l
+; SECURE-PLT: bl printf+32768@PLT
+; NO-SECURE-PLT-NOT: addis 30, 30, .LTOC-.L0$pb@ha
+; NO-SECURE-PLT-NOT: addi 30, 30, .LTOC-.L0$pb@l
+; NO-SECURE-PLT-NOT: bl printf+32768@PLT
 No newline at end of file